Commit Graph

174557 Commits

Author SHA1 Message Date
Alp Toker
6ac2cd01d2 Rename SourceManager::createFileIDForMemBuffer()
It makes more sense to just overload createFileID().

Gardening only.

llvm-svn: 209002
2014-05-16 17:23:01 +00:00
Chad Rosier
d978ca0308 [ARM64] Increases the Sched Model accuracy for Cortex-A53.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D3769

llvm-svn: 209001
2014-05-16 17:15:33 +00:00
David Majnemer
78910fc4da InstSimplify: Improve handling of ashr/lshr
Summary:
Analyze the range of values produced by ashr/lshr cst, %V when it is
being used in an icmp.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3774

llvm-svn: 209000
2014-05-16 17:14:03 +00:00
David Majnemer
ea8d5dbf24 InstSimplify: Optimize using dividend in sdiv
Summary:
The dividend in an sdiv tells us the largest and smallest possible
results.  Use this fact to optimize comparisons against an sdiv with a
constant dividend.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3795

llvm-svn: 208999
2014-05-16 16:57:04 +00:00
Tilmann Scheller
83c5743650 [ARM64] Fix wrong comment in load/store optimization pass.
ldr x1, [x0, #64]
add x0, x0, #64
 ->
ldr x1, [x0], #64

is not a valid transformation, the correct transformation (and what the code actually does) is:

ldr x1, [x0, #64]
add x0, x0, #64
 ->
ldr x1, [x0, #64]!

llvm-svn: 208998
2014-05-16 16:50:13 +00:00
David Blaikie
4a3b84d2f5 DwarfDebug: Refactor AT_ranges/AT_high_pc+AT_low_pc emission into helper function.
llvm-svn: 208997
2014-05-16 16:42:40 +00:00
Simon Atanasyan
b83f380ae4 [yaml2obj][ELF] Add an optional Size field to the YAML section declaration.
Now the only method to configure ELF section's content and size is to assign
a hexadecimal string to the `Content` field. Unfortunately this way is
completely useless when you need to declare a really large section.

To solve this problem this patch adds one more optional field `Size`
to the `RawContentSection` structure. When yaml2obj generates an ELF file
it uses the following algorithm:
1. If both `Content` and `Size` fields are missed create an empty section.
2. If only `Content` field is missed take section length from the `Size`
   field and fill the section by zero.
3. If only `Size` field is missed create a section using data from
   the `Content` field.
4. If both `Content` and `Size` fields are provided validate that the `Size`
   value is not less than size of `Content` data. Than take section length
   from the `Size`, fill beginning of the section by `Content` and the rest
   by zero.

Examples
--------
* Create a section 0x10000 bytes long filled by zero
  Name: .data
  Type: SHT_PROGBITS
  Flags: [ SHF_ALLOC ]
  Size: 0x10000

* Create a section 0x10000 bytes long starting from 'CA' 'FE' 'BA' 'BE'
  Name: .data
  Type: SHT_PROGBITS
  Flags: [ SHF_ALLOC ]
  Content: CAFEBABE
  Size: 0x10000

The patch reviewed by Michael Spencer.

llvm-svn: 208995
2014-05-16 16:01:00 +00:00
James Molloy
a70697e10e Re-enable inline memcpy expansion for Thumb1.
Patch by Moritz Roth!

llvm-svn: 208994
2014-05-16 14:24:22 +00:00
Rafael Espindola
a800445710 Small dyn_cast and auto cleanup.
llvm-svn: 208993
2014-05-16 14:22:33 +00:00
James Molloy
556763d2ef Fix the Load/Store optimization pass to work with Thumb1.
Patch by Moritz Roth!

llvm-svn: 208992
2014-05-16 14:14:30 +00:00
James Molloy
92a15078f1 Enable the Load/Store optimization pass for Thumb1 but make it return immediately for now.
Patch by Moritz Roth!

llvm-svn: 208991
2014-05-16 14:11:38 +00:00
James Molloy
bb73c23ffa Fix a few comment typos and style issues.
Patch by Moritz Roth!

llvm-svn: 208990
2014-05-16 14:08:46 +00:00
Timur Iskhodzhanov
37c00b4b19 [ASan/Win] Refactor __interception::OverrideFunction a bit, allow the orig_old_func parameter to be zero
Reviewed at http://reviews.llvm.org/D3798

llvm-svn: 208989
2014-05-16 14:04:57 +00:00
Alp Toker
77273fc52a Tooling: use stderr, not stdout for missing command line messages
Matches other tooling output that use stderr.

llvm-svn: 208988
2014-05-16 13:45:29 +00:00
Zoran Jovanovic
6110e3bce6 [mips][mips64r6] Add SELEQZ and SELNEZ instructions
Differential Revision: http://reviews.llvm.org/D3743

llvm-svn: 208987
2014-05-16 13:40:57 +00:00
NAKAMURA Takumi
81774baf4d Initializer list is unavailable. Use the constructor instead.
llvm-svn: 208986
2014-05-16 13:37:20 +00:00
NAKAMURA Takumi
2dd94635d4 clang-tidy/misc/UseOverride.cpp: Appease targeting msvc.
With IsLateTemplateParsed, FunctionDecl::doesThisDeclarationHaveABody() returns True regardless of Body.

llvm-svn: 208985
2014-05-16 13:37:08 +00:00
Rafael Espindola
9750ce7ebd Update for llvm API change.
llvm-svn: 208984
2014-05-16 13:34:28 +00:00
Rafael Espindola
4fe0094fd1 Change the GlobalAlias constructor to look a bit more like GlobalVariable.
This is part of the fix for pr10367. A GlobalAlias always has a pointer type,
so just have the constructor build the type.

llvm-svn: 208983
2014-05-16 13:34:04 +00:00
Deepak Panickal
95442c445f Do not require the triple to be hard-coded
llvm-svn: 208982
2014-05-16 13:26:45 +00:00
Zoran Jovanovic
52c56b93e5 [mips][mips64r6] Add Compact indexed jumps.
Differential Revision: http://reviews.llvm.org/D3707

llvm-svn: 208981
2014-05-16 13:19:46 +00:00
Yaron Keren
152172009a Fix hardcoded slash to native path seperator which was exposed from llvm::sys::path.
http://reviews.llvm.org/D3687

llvm-svn: 208980
2014-05-16 13:16:30 +00:00
Alexander Kornienko
3ab3467cef Update clang-tidy documentation.
Summary:
Updated the help message, updated description of -checks=, removed
mentions of -disable-checks.

Reviewers: klimek

Reviewed By: klimek

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D3793

llvm-svn: 208979
2014-05-16 13:07:18 +00:00
Rafael Espindola
5a52b9f139 Revert "Implement global merge optimization for global variables."
This reverts commit r208934.

The patch depends on aliases to GEPs with non zero offsets. That is not
supported and fairly broken.

The good news is that GlobalAlias is being redesigned and will have support
for offsets, so this patch should be a nice match for it.

llvm-svn: 208978
2014-05-16 13:02:18 +00:00
Zoran Jovanovic
5a8c1e2900 [mips][mips64r6] Add Compact zero-compare branch-and-link instructions
Differential Revision: http://reviews.llvm.org/D3718

llvm-svn: 208977
2014-05-16 12:27:19 +00:00
Stepan Dyatkovskiy
948366ac0b MergeFunctions Pass, introduced total ordering among GEP operations.
Patch replaces old isEquivalentGEP implementation, and changes type of
comparison result from bool (equal or not) to {-1, 0, 1} (less, equal, greater).

This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208976
2014-05-16 11:55:02 +00:00
NAKAMURA Takumi
9ba87f4bfa MC: Add DwarfTypesDWOSection also to MCCOFF.
llvm-svn: 208975
2014-05-16 11:14:51 +00:00
Zoran Jovanovic
3c8869dc6a [mips][mips64r6] Add compact branch instructions
Differential Revision: http://reviews.llvm.org/D3691

llvm-svn: 208974
2014-05-16 11:03:45 +00:00
Stepan Dyatkovskiy
fa6820a035 MergeFunctions Pass, introduced total ordering among operations.
Patch replaces old isEquivalentOperation implementation, and changes type of
comparison result from bool (equal or not) to {-1, 0, 1} (less, equal, greater).

This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208973
2014-05-16 11:02:22 +00:00
Deepak Panickal
6f9c468102 Initial commit of LLDB Machine Interface Frontend.
- Tested with Eclipse, likely to work with other GDB/MI compatible GUIs.
- Some but not all MI commands have been implemented. See MIReadme.txt for more info.
- Written from scratch, no GPL code, based on LLDB Public API.
- Built for Linux, Windows and OSX. Tested on Linux and Windows.
- GDB/MI Command Reference, https://sourceware.org/gdb/onlinedocs/gdb/GDB_002fMI.html

llvm-svn: 208972
2014-05-16 10:51:01 +00:00
Zoran Jovanovic
d04688d1c6 [mips][mips64r6] Add LWPC and LWUPC instructions
Differential Revision: http://reviews.llvm.org/D3788

llvm-svn: 208971
2014-05-16 10:27:10 +00:00
Zoran Jovanovic
027a5df93d [mips][mips64r6] Add Floating Point Compare setting Mask - CMP.condn.fmt
Differential Revision: http://reviews.llvm.org/D3750

llvm-svn: 208970
2014-05-16 09:48:29 +00:00
Tim Northover
5896b066e6 TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.

This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.

There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:

+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"

llvm-svn: 208969
2014-05-16 09:42:04 +00:00
Tim Northover
28aef9e05d ARM64: disable printing of "fcmXY ..., #0" aliases
The canonical syntax is "fcmXY ..., #0.0".

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208968
2014-05-16 09:41:48 +00:00
Tim Northover
488e6206df AArch64: disable printing of add/sub alias
This alias appears not to have an appropriate PrintMethod. Normally, I'd look
into it, but since AArch64 is disappearing soon it's probably not worth it.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208967
2014-05-16 09:41:43 +00:00
Tim Northover
a670f746a3 Sparc: disable printing of jmp/call aliases (C++ does it)
These aliases are handled entirely in C++ and only having TableGen InstAliases
for some of them was confusing LLVM.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208966
2014-05-16 09:41:39 +00:00
Tim Northover
ba101dd35d Sparc: disable printing on longer "brX,pt" aliases
This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208965
2014-05-16 09:41:35 +00:00
Tim Northover
fe6591ed77 Mips: don't print subu alias for addiu
Certainly not without having a custom PrintMethod to invert the immediate
beforehand. But probably not at all.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208964
2014-05-16 09:41:30 +00:00
Tim Northover
8f8df324f3 X86: disable printing of bare "mov" aliases
In AT&T syntax, we should probably print the full "movl" or "movw". TableGen
used to ignore these aliases because it was miscounting the number of operands.
This fixes the issue.

This will be tested when the TableGen "should I print this Alias"
heuristic is fixed (very soon).

llvm-svn: 208963
2014-05-16 09:41:26 +00:00
Tim Northover
32dcf2d042 AArch64: disable printing of MOV -> MOVZ aliases
Actually, MOV sometimes is canonical, but for now this is a better
approximation than what's there.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208962
2014-05-16 09:41:21 +00:00
Tim Northover
3e1c7e0198 ARM64: disable printing of swapped compare-mask aliases
You can perform (say) an fcmle operation by swapping the operands on an fcmge,
but it shouldn't be printed like that.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208961
2014-05-16 09:41:16 +00:00
Tim Northover
5420649590 ARM64: disable printing of LDUR -> LDR aliases
We accept "ldr w3, [x1, #-1]" as a convenience, but we should still print the
canonical "ldur" form.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208960
2014-05-16 09:41:12 +00:00
Tim Northover
5763670b09 ARM64: give TST aliases priority over ANDS.
If an ANDS instruction has Rd == ZR it should be printed as TST since
its only effect is on the flags register NZCV.

This will be tested when the TableGen "should I print this Alias"
heuristic is fixed (very soon).

llvm-svn: 208959
2014-05-16 09:41:08 +00:00
Tim Northover
106ac4830e ARM64: give MOV priority over shorter ORR when printing aliases.
MOV is almost always the right thing to print if possile. People understand it.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208958
2014-05-16 09:41:03 +00:00
Tim Northover
51b4de90f2 ARM64: give NEG priority over SUB when printing aliases.
For example, the full instruction "sub w0, wzr, w1, uxtw" could print as either
"neg w0, w1" or "sub w0, wzr, w1". The former is better.

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208957
2014-05-16 09:40:58 +00:00
Tim Northover
9c2b4c29ab ARM64: disable printing of "lslv" type aliases
You can write "lslv w0, w1, w2" (probably for legacy reasons), but it should be
printed as simply "lsl".

This will be tested when the TableGen "should I print this Alias" heuristic is
fixed (very soon).

llvm-svn: 208956
2014-05-16 09:40:52 +00:00
Hao Liu
8579f0d4d1 [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.
llvm-svn: 208955
2014-05-16 09:39:02 +00:00
Daniel Jasper
2378ebd537 Initial version of clang-tidy check to use override instead of virual.
Review: http://reviews.llvm.org/D3688
llvm-svn: 208954
2014-05-16 09:30:09 +00:00
Stepan Dyatkovskiy
5c2cc2506d MergeFunctions Pass, introduced total ordering among function attributes.
This patch belongs to patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).

llvm-svn: 208953
2014-05-16 08:55:34 +00:00
Zoran Jovanovic
b397fea9ab [mips][mips64r6] Add Floating Point Fused Multiply Add Subtract
Differential Revision: http://reviews.llvm.org/D3727

llvm-svn: 208952
2014-05-16 08:42:27 +00:00