Commit Graph

14670 Commits

Author SHA1 Message Date
LLVM GN Syncbot
4d70f5fe13 [gn build] Port 12ca72ba7f 2024-12-04 11:04:05 +00:00
Fraser Cormack
8c46413f34 [vim] Improve iskeyword for LLVM IR (#117905)
This patch sets the 'iskeyword' variable to characters found in LLVM IR
identifiers. Keywords are used in many places in vim, most notably being
treated as word boundaries for commands like 'w' and '*'. The aim with
this is to improve the navigability and editability of LLVM IR files as
now one is able to: skip over entire identifiers with motions (e.g.,
`w/e/b`); yank/delete whole identifiers (e.g., `diw`); highlight/search
for the identifier under the cursor (`*`), etc.

More complicated LLVM identifiers including quotation marks are not
supported. The 'iskeyword' variable is just a list of characters, not a
regex, and including quotation marks and all the characters permitted in
quoted identifiers would expand the scope to almost everything and
become less usable. These types of identifiers are rare by comparison.

Note that this does change how words are considered across the entire
LLVM IR file, so including strings, comments, names, etc. Given that the
majority of editing/navigating LLVM IR is working with and across
values, this is arguably a worthwhile trade-off.
2024-12-04 10:56:55 +00:00
LLVM GN Syncbot
a30f7e190b [gn build] Port 54db16221c 2024-12-04 10:44:27 +00:00
LLVM GN Syncbot
adf892d743 [gn build] Port 4b5e7fa4de 2024-12-04 10:31:57 +00:00
Sam Elliott
73731d6873 [llvm-tblgen] Increase Coverage Index Size (#118329) 2024-12-04 09:19:13 +00:00
LLVM GN Syncbot
5e7c88bf4c [gn build] Port 9c9d4b9e73 2024-12-04 05:48:56 +00:00
LLVM GN Syncbot
67d8e1754d [gn build] Port 259bdc0033 2024-12-04 00:51:06 +00:00
LLVM GN Syncbot
b206ba1867 [gn build] Port 0c8928d456 2024-12-03 22:26:48 +00:00
LLVM GN Syncbot
7417ba6730 [gn build] Port fef54d0393 2024-12-03 21:12:38 +00:00
LLVM GN Syncbot
69e9ceb043 [gn build] Port 80987ef4b6 2024-12-03 21:12:37 +00:00
LLVM GN Syncbot
4b9bf660f3 [gn build] Port acf3b1aa93 2024-12-03 18:45:30 +00:00
Mason Remy
0c6457b781 [LLVM][TableGen] Refine overloaded intrinsic suffix check (#117957)
Previously the check comments indicated that [pi][0-9]+ would match as a
type suffix, however the check itself was looking for [pi][0-9]* and
hence an 'i' suffix in isolation was being considered as a type suffix
despite it not having a bitwidth.

This change makes the check consistent with the comment and looks for
[pi][0-9]+
2024-12-03 13:33:15 -05:00
Nico Weber
897dbdeab7 [gn] port 51003076eb 2024-12-02 19:55:46 -05:00
Paschalis Mpeis
51003076eb Reapply [BOLT] DataAggregator support for binaries with multiple text segments (#118023)
When a binary has multiple text segments, the Size is computed as the
difference of the last address of these segments from the BaseAddress.
The base addresses of all text segments must be the same.

Introduces flag 'perf-script-events' for testing, which allows passing
perf events without BOLT having to parse them by invoking 'perf script'.
The flag is used to pass a mock perf profile that has two memory
mappings for a mock binary that has two text segments. The mapping
size is updated as `parseMMapEvents` now processes all text segments.
2024-12-02 09:20:40 +00:00
Adam Yang
0a44b24d66 [DXIL] Add GroupMemoryBarrierWithGroupSync intrinsic (#114349)
fixes #112974
partially fixes #70103

An earlier version of this change was reverted so some issues could be fixed.

### Changes
- Added new tablegen based way of lowering dx intrinsics to DXIL ops.
- Added int_dx_group_memory_barrier_with_group_sync intrinsic in
IntrinsicsDirectX.td
- Added expansion for int_dx_group_memory_barrier_with_group_sync in
DXILIntrinsicExpansion.cpp`
- Added DXIL backend test case

### Related PRs
* [[clang][HLSL] Add GroupMemoryBarrierWithGroupSync intrinsic
#111883](https://github.com/llvm/llvm-project/pull/111883)
* [[SPIRV] Add GroupMemoryBarrierWithGroupSync intrinsic
#111888](https://github.com/llvm/llvm-project/pull/111888)
2024-12-01 22:31:40 -08:00
Jinsong Ji
2e30df740e [TableGen] Fix validateOperandClass for non Phyical Reg (#118146)
https://github.com/llvm/llvm-project/commit/b71704436e61
Rewrote the register operands handling,
but the Table only contains physical regs, we will SEGV when there are
non physical regs.

---------

Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>
2024-11-30 12:07:15 -05:00
Joseph Huber
4148aa63e2 [Reland][Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)
Summary:
When building a project in a runtime mode, the compilation database is a
separate CMake invocation. So its `compile_commands.json` file will be
placed elsewhere in the `runtimes/runtime-bins` directory. This is
somewhat annoying for ongoing development when a runtimes build is
necessary. This patch adds some CMake magic to merge the two files.

Fixed issue w/ standalone runtimes build by checking if the LLVM src and
CMake src are the same.
2024-11-30 08:50:08 -06:00
LLVM GN Syncbot
b22cc5a650 [gn build] Port 8ac2b77a11 2024-11-29 23:55:28 +00:00
LLVM GN Syncbot
9b163d2ee7 [gn build] Port 01a15dca09 2024-11-29 05:26:23 +00:00
LLVM GN Syncbot
eb42e94d97 [gn build] Port b96e7570c9 2024-11-29 02:46:55 +00:00
LLVM GN Syncbot
bfa6c9a959 [gn build] Port 6cbc37383f 2024-11-29 02:46:54 +00:00
LLVM GN Syncbot
958ab3a4a5 [gn build] Port 53326ee0cf 2024-11-29 02:46:53 +00:00
LLVM GN Syncbot
7c5300e734 [gn build] Port 45b567be8d 2024-11-29 02:46:52 +00:00
Nico Weber
c2171d7486 [gn] port fb3765959f 2024-11-28 21:46:01 -05:00
Louis Dionne
b207a17ea0 Revert "[Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)"
This reverts commit 054f914741, which was
found to break the runtimes build.
2024-11-28 11:21:01 -05:00
Rafael Eckstein
2a6e5896a5 [MergeFunctions] Add support to run the pass over a set of function pointers (#111045)
This modification will enable the usage of `MergeFunctions` as a
standalone library. Currently, `MergeFunctions` can only be applied to
an entire module. By adopting this change, developers will gain the
flexibility to reuse the `MergeFunctions` code within their own
projects, choosing which functions to merge; hence, promoting code
reusability. Notice that this modification will not break backward
compatibility, because `MergeFunctions` will still work as a pass after
the modification.
2024-11-28 16:18:52 +01:00
Jay Foad
89b08c8ee7 [TableGen] Simplify generated code for isSubclass (#117351)
Implement isSubclass with direct lookup into some tables instead of
nested switches.

Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
2024-11-28 08:52:02 +00:00
Joseph Huber
054f914741 [Runtimes] Merge 'compile_commands.json' files from runtimes build (#116303)
Summary:
When building a project in a runtime mode, the compilation database is a
separate CMake invocation. So its `compile_commands.json` file will be
placed elsewhere in the `runtimes/runtime-bins` directory. This is
somewhat annoying for ongoing development when a runtimes build is
necessary. This patch adds some CMake magic to merge the two files.
2024-11-27 20:14:26 -06:00
LLVM GN Syncbot
2e9469885d [gn build] Port 87503fa51c 2024-11-27 18:16:38 +00:00
Jay Foad
b71704436e [TableGen] Simplify generated code for validateOperandClass (#117889)
Implement the register operand handling in validateOperandClass with a
table lookup instead of a potentially huge switch.

Part of the motivation for this is improving compile time when clang-18
is used as a host compiler, since it seems to have trouble with very
large switch statements.
2024-11-27 16:49:35 +00:00
LLVM GN Syncbot
66126c350f [gn build] Port 318c69de52 2024-11-27 13:42:33 +00:00
Sander de Smalen
318c69de52 Reland "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)"
The issue with slow compile-time was caused by an assert in
AArch64RegisterInfo.cpp. The assert invokes 'checkAllSuperRegsMarked'
after adding all the reserved registers. This call gets very expensive
after adding the _HI registers due to the way the function searches
in the 'Exception' list, which is expected to be a small list but isn't
(the patch added 190 _HI regs).

It was possible to rewrite the code in such a way that the _HI registers
are marked as reserved after the check. This makes the problem go away
entirely and restores compile-time to what it was before (tested for
`check-runtimes`, which previously showed a ~5x slowdown).

This reverts commits:
  1434d2ab21
  2704647fb7
2024-11-27 13:31:59 +00:00
LLVM GN Syncbot
cc113102c6 [gn build] Port 5147e5941d 2024-11-27 01:38:39 +00:00
LLVM GN Syncbot
e1af76cad2 [gn build] Port 7ae61a36f9 2024-11-26 23:00:14 +00:00
LLVM GN Syncbot
105b7803ea [gn build] Port f9dca5bdbb 2024-11-26 21:18:06 +00:00
Peter Collingbourne
9118d3a564 gn build: Fix port of 3cb28522ba
COMPILER_RT_EXEC_OUTPUT_DIR is expected to be the path where
hwasan_symbolize is installed, i.e. the bin subdirectory of the
build directory, but we were incorrectly setting it to the install
location of the runtime libraries. Fix it.
2024-11-26 13:17:23 -08:00
Nico Weber
c9562b181c [gn] port 3cb28522ba 2024-11-26 15:10:48 -05:00
Nico Weber
5683fc5cc0 [gn] port a5dd646360 2024-11-26 14:05:38 -05:00
Hans Wennborg
537343dea4 Revert "[BOLT] DataAggregator support for binaries with multiple text segments (#92815)"
This caused test failures, see comment on the PR:

  Failed Tests (2):
    BOLT-Unit :: Core/./CoreTests/AArch64/MemoryMapsTester/MultipleSegmentsMismatchedBaseAddress/0
    BOLT-Unit :: Core/./CoreTests/X86/MemoryMapsTester/MultipleSegmentsMismatchedBaseAddress/0

> When a binary has multiple text segments, the Size is computed as the
> difference of the last address of these segments from the BaseAddress.
> The base addresses of all text segments must be the same.
>
> Introduces flag 'perf-script-events' for testing. It allows passing perf events
> without BOLT having to parse them using 'perf script'. The flag is used to
> pass a mock perf profile that has two memory mappings for a mock binary
> that has two text segments. The size of the mapping is updated as this
> change `parseMMapEvents` processes all text segments.

This reverts commit 4b71b3782d.
2024-11-26 14:59:30 +01:00
Paschalis Mpeis
4b71b3782d [BOLT] DataAggregator support for binaries with multiple text segments (#92815)
When a binary has multiple text segments, the Size is computed as the
difference of the last address of these segments from the BaseAddress.
The base addresses of all text segments must be the same.

Introduces flag 'perf-script-events' for testing. It allows passing perf events
without BOLT having to parse them using 'perf script'. The flag is used to
pass a mock perf profile that has two memory mappings for a mock binary
that has two text segments. The size of the mapping is updated as this
change `parseMMapEvents` processes all text segments.
2024-11-25 13:12:43 +00:00
Jay Foad
535247841d [TableGen] Remove comments from generated validateOperandClass (#117352)
This generated comments like:

  // 'BoolReg' class
  case MCK_BoolReg: {

which seem redundant because the name is always repeated on the next
line as part of the MCK_ enumerator.
2024-11-25 12:11:01 +00:00
Sergei Barannikov
b3363104d3 [UTC] Add support for Xtensa (#117441)
Regenerate the failing test as well.
2024-11-23 20:43:05 +03:00
LLVM GN Syncbot
0ffdaf445e [gn build] Port 1434d2ab21 2024-11-22 21:58:46 +00:00
LLVM GN Syncbot
094ef38b12 [gn build] Port 028d41d7cf 2024-11-22 21:58:45 +00:00
Vitaly Buka
1434d2ab21 Revert "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)" (#117307)
Details in #114827

This reverts commit c1c68baf7e.
2024-11-22 11:48:25 -08:00
Simon Pilgrim
29f11f0a32 [X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)
More canonicalization of the instruction names to make the predictable - more closely matches VRNDSCALEP / VROUND equivalent instructions
2024-11-22 17:45:30 +00:00
Jay Foad
285754d799 [TableGen] Fix closing brace indentation in validateOperandClass 2024-11-22 17:42:39 +00:00
Mehdi Amini
c4aa83840b Improve slightly the pre-commit git hook usage of the auto-format helper (#117326)
The default mode does not provide a way to see the actual failure of the
formatters without modifying the code. Instead offer the user the option
to rerun with a `FORMAT_HOOK_VERBOSE=1` environment variable to print
the actual formatting diff.
2024-11-22 16:58:12 +01:00
Pengcheng Wang
4da960b898 [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)
We can get these information via `sys_riscv_hwprobe`.

This can be used to implement `__builtin_cpu_is`.
2024-11-22 22:58:54 +08:00
Mikhail Goncharov
d1dae1e861 Revert "[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202)" chain
This reverts commit b36fcf4f49.
This reverts commit c11b6b1b8a.
This reverts commit 775148f236.

multiple bot build breakages, e.g. https://lab.llvm.org/buildbot/#/builders/3/builds/8076
2024-11-22 14:09:13 +01:00