caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
automated-release
clang-p2996/llvm/test/Transforms/AggressiveInstCombine
History
Craig Topper 96336b2330 [AggressiveInstCombine] Improve popcount matching if the input has known zero bits (#142501) 
If the input has known zero bits, InstCombine may have simplied one
of the expected And masks. Teach AggressiveInstCombine to use
MaskedValueIsZero to recover these missing bits.
    
Fixes #142042.
2025-06-03 12:56:53 -07:00
..
AArch64
[AggressiveInstCombine] Add test for shifts from or chains. NFC
2025-05-09 09:29:50 +01:00
ARM
…
X86
…
dbgloc-memchr.ll
…
funnel.ll
…
inline-strcmp-debugloc.ll
…
logic-combine.ll
…
lower-table-based-cttz-basics.ll
[AggressiveInstCombine] Check GEP nusw, not inbounds (#139708)
2025-05-22 17:43:29 +01:00
lower-table-based-cttz-dereferencing-pointer.ll
…
lower-table-based-cttz-non-argument-value.ll
…
lower-table-based-cttz-zero-element.ll
…
masked-cmp.ll
…
memchr.ll
…
negative-lower-table-based-cttz.ll
…
or-shift-chain.ll
[AggressiveInstcombine] Fold away shift in or reduction chain. (#137875)
2025-05-13 10:33:38 +01:00
patterned-load.ll
[AggressiveInstCombine] Check GEP nusw, not inbounds (#139708)
2025-05-22 17:43:29 +01:00
popcount.ll
[AggressiveInstCombine] Improve popcount matching if the input has known zero bits (#142501)
2025-06-03 12:56:53 -07:00
pr50555.ll
…
rotate.ll
…
strncmp-1.ll
…
strncmp-2.ll
…
trunc_ashr.ll
…
trunc_assume.ll
…
trunc_const_expr.ll
…
trunc_lshr.ll
…
trunc_multi_uses.ll
…
trunc_phi.ll
…
trunc_select_cmp.ll
…
trunc_select.ll
…
trunc_shl.ll
…
trunc_udivrem.ll
…
trunc_unreachable_bb.ll
…
trunc_vector_instrs.ll
…
vector-or-load.ll
…