c56f1d34bc
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
llvm-svn: 169910
267 lines
10 KiB
C++
267 lines
10 KiB
C++
//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPCMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCBaseInfo.h"
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#include "MCTargetDesc/PPCFixupKinds.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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class PPCMCCodeEmitter : public MCCodeEmitter {
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PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCSubtargetInfo &STI;
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Triple TT;
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public:
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PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
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MCContext &ctx)
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: STI(sti), TT(STI.getTargetTriple()) {
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}
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~PPCMCCodeEmitter() {}
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bool is64BitMode() const {
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return (STI.getFeatureBits() & PPC::Feature64Bit) != 0;
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}
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bool isSVR4ABI() const {
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return TT.isMacOSX() == 0;
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}
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unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getTLSOffsetEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
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// BL8_NOPELF and BLA8_NOP_ELF is both size of 8 bacause of the
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// following 'nop'.
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unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
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unsigned Opcode = MI.getOpcode();
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if (Opcode == PPC::BL8_NOP_ELF || Opcode == PPC::BLA8_NOP_ELF)
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Size = 8;
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// Output the constant in big endian byte order.
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int ShiftValue = (Size * 8) - 8;
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for (unsigned i = 0; i != Size; ++i) {
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OS << (char)(Bits >> ShiftValue);
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Bits <<= 8;
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCMCCodeEmitter(MCII, STI, Ctx);
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}
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unsigned PPCMCCodeEmitter::
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getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_br24));
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// For special TLS calls, add another fixup for the symbol. Apparently
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// BL8_NOP_ELF and BL8_NOP_ELF_TLSGD are sufficiently similar that TblGen
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// will not generate a separate case for the latter, so this is the only
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// way to get the extra fixup generated.
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if (MI.getOpcode() == PPC::BL8_NOP_ELF_TLSGD) {
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const MCOperand &MO2 = MI.getOperand(OpNo+1);
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Fixups.push_back(MCFixup::Create(0, MO2.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_tlsgd));
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}
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return 0;
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}
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unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_brcond14));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_ha16));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Encode (imm, reg) as a memri, which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
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// Add a fixup for the displacement field.
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if (isSVR4ABI() && is64BitMode())
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_toc16));
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else
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Encode (imm, reg) as a memrix, which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
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// Add a fixup for the branch target.
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if (isSVR4ABI() && is64BitMode())
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_toc16_ds));
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else
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo14));
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getTLSOffsetEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// Add a fixup for the GOT displacement to the TLS block offset.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_toc16_ds));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the TLS register, which simply provides a relocation
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// hint to the linker that this statement is part of a relocation sequence.
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// Return the thread-pointer register's encoding.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_tlsreg));
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return getPPCRegisterNumbering(PPC::X13);
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}
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unsigned PPCMCCodeEmitter::
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get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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assert((MI.getOpcode() == PPC::MTCRF ||
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MI.getOpcode() == PPC::MFOCRF ||
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MI.getOpcode() == PPC::MTCRF8) &&
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(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
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return 0x80 >> getPPCRegisterNumbering(MO.getReg());
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}
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unsigned PPCMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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// MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
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// The GPR operand should come through here though.
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assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
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MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
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return getPPCRegisterNumbering(MO.getReg());
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}
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assert(MO.isImm() &&
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"Relocation required in an instruction that we cannot encode!");
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return MO.getImm();
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}
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#include "PPCGenMCCodeEmitter.inc"
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