94 lines
3.5 KiB
LLVM
94 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=IC1 %s
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; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=IC2 %s
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define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
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; IC1-LABEL: define void @switch4_default_common_dest_with_case(
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; IC1-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
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; IC1-NEXT: [[ENTRY:.*]]:
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; IC1-NEXT: br label %[[LOOP_HEADER:.*]]
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; IC1: [[LOOP_HEADER]]:
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; IC1-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; IC1-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV]], align 1
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; IC1-NEXT: switch i8 [[L]], label %[[DEFAULT:.*]] [
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; IC1-NEXT: i8 -12, label %[[IF_THEN_1:.*]]
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; IC1-NEXT: i8 13, label %[[IF_THEN_2:.*]]
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; IC1-NEXT: i8 0, label %[[DEFAULT]]
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; IC1-NEXT: ]
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; IC1: [[IF_THEN_1]]:
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; IC1-NEXT: store i8 42, ptr [[PTR_IV]], align 1
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; IC1-NEXT: br label %[[LOOP_LATCH]]
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; IC1: [[IF_THEN_2]]:
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; IC1-NEXT: store i8 0, ptr [[PTR_IV]], align 1
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; IC1-NEXT: br label %[[LOOP_LATCH]]
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; IC1: [[DEFAULT]]:
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; IC1-NEXT: store i8 2, ptr [[PTR_IV]], align 1
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; IC1-NEXT: br label %[[LOOP_LATCH]]
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; IC1: [[LOOP_LATCH]]:
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; IC1-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 1
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; IC1-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
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; IC1-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; IC1: [[EXIT]]:
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; IC1-NEXT: ret void
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;
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; IC2-LABEL: define void @switch4_default_common_dest_with_case(
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; IC2-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
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; IC2-NEXT: [[ENTRY:.*]]:
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; IC2-NEXT: br label %[[LOOP_HEADER:.*]]
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; IC2: [[LOOP_HEADER]]:
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; IC2-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; IC2-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV]], align 1
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; IC2-NEXT: switch i8 [[L]], label %[[DEFAULT:.*]] [
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; IC2-NEXT: i8 -12, label %[[IF_THEN_1:.*]]
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; IC2-NEXT: i8 13, label %[[IF_THEN_2:.*]]
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; IC2-NEXT: i8 0, label %[[DEFAULT]]
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; IC2-NEXT: ]
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; IC2: [[IF_THEN_1]]:
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; IC2-NEXT: store i8 42, ptr [[PTR_IV]], align 1
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; IC2-NEXT: br label %[[LOOP_LATCH]]
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; IC2: [[IF_THEN_2]]:
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; IC2-NEXT: store i8 0, ptr [[PTR_IV]], align 1
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; IC2-NEXT: br label %[[LOOP_LATCH]]
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; IC2: [[DEFAULT]]:
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; IC2-NEXT: store i8 2, ptr [[PTR_IV]], align 1
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; IC2-NEXT: br label %[[LOOP_LATCH]]
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; IC2: [[LOOP_LATCH]]:
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; IC2-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 1
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; IC2-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
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; IC2-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; IC2: [[EXIT]]:
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; IC2-NEXT: ret void
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;
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entry:
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br label %loop.header
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loop.header:
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%ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
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%l = load i8, ptr %ptr.iv, align 1
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switch i8 %l, label %default [
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i8 -12, label %if.then.1
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i8 13, label %if.then.2
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i8 0, label %default
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]
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if.then.1:
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store i8 42, ptr %ptr.iv, align 1
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br label %loop.latch
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if.then.2:
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store i8 0, ptr %ptr.iv, align 1
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br label %loop.latch
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default:
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store i8 2, ptr %ptr.iv, align 1
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br label %loop.latch
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loop.latch:
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%ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 1
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%ec = icmp eq ptr %ptr.iv.next, %end
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br i1 %ec, label %exit, label %loop.header
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exit:
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ret void
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}
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