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clang-p2996/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
Mateja Marjanovic 595a08847a [AMDGPU] Add support for new LLVM vector types 
Add VReg, AReg and SReg on AMDGPU for bit widths: 288, 320, 352 and 384.

Differential Revision: https://reviews.llvm.org/D138205
2022-11-29 17:02:04 +01:00

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