Ayke van Laethem 9592920890 [AVR] Optimize 32-bit shifts: optimize REG_SEQUENCE ...

This pseudo-instruction stores two small (8-bit) registers into one wide
(16-bit) register. But apparently the order matters a lot to the
register allocator.
This patch changes the order of inserting the registers to optimize for
the best register allocation in the tests of shift32.ll. It might be
detrimental in other cases, but keeping the registers in the same
physical register seems like it would be a common case.

Differential Revision: https://reviews.llvm.org/D140573

2023-01-08 20:05:31 +01:00

96 KiB

Raw Blame History

View Raw