d6c0ef7887
The Power ISA defined l[bhwdq]arx as both base and extended mnemonics. The base mnemonic takes the EH bit as an operand and the extended mnemonic omits it, making it implicitly zero. The existing implementation only handles the base mnemonic when EH is 1 and internally produces a different instruction. There are historical reasons for this. This patch simply removes the limitation introduced by this implementation that disallows the base mnemonic with EH = 0 in the ASM parser. This resolves an issue that prevented some files in the Linux kernel from being built with -fintegrated-as. Also fix a crash if the value is not an integer immediate.
146 lines
3.6 KiB
ArmAsm
146 lines
3.6 KiB
ArmAsm
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# RUN: not llvm-mc -triple powerpc64-unknown-unknown < %s 2> %t
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# RUN: FileCheck < %t %s
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# RUN: not llvm-mc -triple powerpc64le-unknown-unknown < %s 2> %t
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# RUN: FileCheck < %t %s
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# Register operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: add 32, 32, 32
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add 32, 32, 32
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# CHECK: error: invalid register name
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# CHECK-NEXT: add %r32, %r32, %r32
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add %r32, %r32, %r32
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# TLS register operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: add 3, symbol@tls, 4
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add 3, symbol@tls, 4
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: subf 3, 4, symbol@tls
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subf 3, 4, symbol@tls
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# Unsigned 1-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: mtmsr 1, 2
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mtmsr 1, 2
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: mtmsrd 1, 2
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mtmsrd 1, 2
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: mtfsf 1, 2, 2, 1
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mtfsf 1, 2, 2, 1
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: mtfsf. 1, 2, 2, 1
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mtfsf. 1, 2, 2, 1
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# Unsigned 2-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: darn 1, 4
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darn 1, 4
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: wait 4
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wait 4
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: sync 4
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sync 4
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# Unsigned 3-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: dcbf 0, 1, 8
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dcbf 0, 1, 8
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# Signed 16-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: addi 1, 0, -32769
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addi 1, 0, -32769
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: addi 1, 0, 32768
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addi 1, 0, 32768
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# Unsigned 16-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ori 1, 2, -1
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ori 1, 2, -1
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ori 1, 2, 65536
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ori 1, 2, 65536
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# Signed 16-bit immediate operands (extended range for addis)
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# CHECK: error: invalid operand for instruction
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addis 1, 0, -65537
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# CHECK: error: invalid operand for instruction
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addis 1, 0, 65536
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# D-Form memory operands
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# CHECK: error: invalid register number
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# CHECK-NEXT: lwz 1, 0(32)
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lwz 1, 0(32)
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# CHECK: error: invalid register name
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# CHECK-NEXT: lwz 1, 0(%r32)
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lwz 1, 0(%r32)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: lwz 1, -32769(2)
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lwz 1, -32769(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: lwz 1, 32768(2)
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lwz 1, 32768(2)
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# CHECK: error: invalid register number
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# CHECK-NEXT: ld 1, 0(32)
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ld 1, 0(32)
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# CHECK: error: invalid register name
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# CHECK-NEXT: ld 1, 0(%r32)
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ld 1, 0(%r32)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 1(2)
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ld 1, 1(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 2(2)
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ld 1, 2(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 3(2)
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ld 1, 3(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, -32772(2)
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ld 1, -32772(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 32768(2)
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ld 1, 32768(2)
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# CHECK: error: invalid modifier 'got' (no symbols present)
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addi 4, 3, 123@got
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# CHECK-NEXT: addi 4, 3, 123@got
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: lwarx 1, 2, 3, a
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lwarx 1, 2, 3, a
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