9a26f89316
Currently the DecoderEmitter constructor takes a bunch of string parameters containing bits of code to interpolate. However, there's only two ways it can be called. The one used for most targets which doesn't handle the SoftFail DecoderStatus (not a problem, because they don't use SoftFail). The other mode, which is used for ARM/AArch64, does handle SoftFail, but requires an externally defined helper function in those targets. This is unnecessary complication; remove the parameters, and unify onto a single version which does support SoftFail, defining the helper itself.
88 lines
2.9 KiB
TableGen
88 lines
2.9 KiB
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i64], 0, (add Reg)>;
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def GR64 : RegisterOperand<RegClass>;
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class MyMemOperand<dag sub_ops> : Operand<iPTR> {
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let MIOperandInfo = sub_ops;
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dag Base;
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dag Extension;
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}
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def MemOp16: MyMemOperand<(ops GR64:$reg, i16imm:$offset)>;
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def MemOp32: MyMemOperand<(ops GR64:$reg, i32imm:$offset)>;
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class MyVarInst<MyMemOperand memory_op> : Instruction {
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dag Inst;
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let OutOperandList = (outs GR64:$dst);
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let InOperandList = (ins memory_op:$src);
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}
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def FOO16 : MyVarInst<MemOp16> {
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let Inst = (ascend
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(descend (operand "$dst", 3), 0b01000, (operand "$src.reg", 3)),
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(slice "$src.offset", 15, 0)
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);
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}
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def FOO32 : MyVarInst<MemOp32> {
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let Inst = (ascend
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(descend (operand "$dst", 3), 0b01001, (operand "$src.reg", 3)),
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(slice "$src.offset", 31, 16),
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(slice "$src.offset", 15, 0)
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);
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}
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// CHECK: MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ...
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// CHECK-NEXT: MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12
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// CHECK-NEXT: MCD::OPC_Decode, [[#OPCODE:]], 1, 0, // Opcode: FOO16
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// CHECK-NEXT: MCD::OPC_FilterValue, 9, 4, 0, 0, // Skip to: 21
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// CHECK-NEXT: MCD::OPC_Decode, [[#OPCODE+1]], 1, 1, // Opcode: FOO32
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// CHECK-NEXT: MCD::OPC_Fail,
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// Instruction length table
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// CHECK: 27,
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// CHECK-NEXT: 43,
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// CHECK-NEXT: };
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// CHECK: case 0:
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 11, 16);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: return S;
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// CHECK-NEXT: case 1:
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
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// CHECK-NEXT: if (!Check(S, DecodeRegClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
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// CHECK-NEXT: tmp = 0x0;
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// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 11, 16), 16, 16);
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// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 27, 16), 0, 16);
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// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
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// CHECK-NEXT: return S;
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// CHECK-LABEL: case MCD::OPC_ExtractField: {
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// CHECK: makeUp(insn, Start + Len);
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// CHECK-LABEL: case MCD::OPC_CheckField: {
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// CHECK: makeUp(insn, Start + Len);
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// CHECK-LABEL: case MCD::OPC_Decode: {
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// CHECK: Len = InstrLenTable[Opc];
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// CHECK-NEXT: makeUp(insn, Len);
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