Tim Northover c7ea8048e7 ARM: don't expand atomicrmw inline on Cortex-M0 ...

There's a barrier instruction so that should still be used, but most actual
atomic operations are going to need a platform decision on the correct
behaviour (either nop if single-threaded or OS-support otherwise).

rdar://problem/15287210

llvm-svn: 193399

2013-10-25 09:30:24 +00:00

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