There shall be 1 wait state between M0 write and LDS DMA/LDS_DIRECT use. Differential Revision: https://reviews.llvm.org/D124550
5.0 KiB
5.0 KiB
There shall be 1 wait state between M0 write and LDS DMA/LDS_DIRECT use. Differential Revision: https://reviews.llvm.org/D124550