967dc58ac1
In optimizeCompareInstr, a compare instruction is eliminated by using a record form instruction if possible. If the branch instruction that uses the result of the compare has a static branch hint, the optimization does not happen. This patch makes this optimization happen regardless of the branch hint by splitting branch hint and branch condition before checking the predicate to identify the possible optimizations. Differential Revision: https://reviews.llvm.org/D35801 llvm-svn: 309255
93 lines
3.0 KiB
C++
93 lines
3.0 KiB
C++
//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PowerPC branch predicates.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCPREDICATES_H
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#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCPREDICATES_H
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// GCC #defines PPC on Linux but we use it as our namespace name
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#undef PPC
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// Generated files will use "namespace PPC". To avoid symbol clash,
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// undefine PPC here. PPC may be predefined on some hosts.
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#undef PPC
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namespace llvm {
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namespace PPC {
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/// Predicate - These are "(BI << 5) | BO" for various predicates.
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enum Predicate {
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PRED_LT = (0 << 5) | 12,
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PRED_LE = (1 << 5) | 4,
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PRED_EQ = (2 << 5) | 12,
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PRED_GE = (0 << 5) | 4,
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PRED_GT = (1 << 5) | 12,
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PRED_NE = (2 << 5) | 4,
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PRED_UN = (3 << 5) | 12,
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PRED_NU = (3 << 5) | 4,
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PRED_LT_MINUS = (0 << 5) | 14,
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PRED_LE_MINUS = (1 << 5) | 6,
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PRED_EQ_MINUS = (2 << 5) | 14,
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PRED_GE_MINUS = (0 << 5) | 6,
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PRED_GT_MINUS = (1 << 5) | 14,
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PRED_NE_MINUS = (2 << 5) | 6,
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PRED_UN_MINUS = (3 << 5) | 14,
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PRED_NU_MINUS = (3 << 5) | 6,
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PRED_LT_PLUS = (0 << 5) | 15,
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PRED_LE_PLUS = (1 << 5) | 7,
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PRED_EQ_PLUS = (2 << 5) | 15,
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PRED_GE_PLUS = (0 << 5) | 7,
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PRED_GT_PLUS = (1 << 5) | 15,
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PRED_NE_PLUS = (2 << 5) | 7,
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PRED_UN_PLUS = (3 << 5) | 15,
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PRED_NU_PLUS = (3 << 5) | 7,
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// When dealing with individual condition-register bits, we have simple set
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// and unset predicates.
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PRED_BIT_SET = 1024,
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PRED_BIT_UNSET = 1025
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};
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// Bit for branch taken (plus) or not-taken (minus) hint
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enum BranchHintBit {
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BR_NO_HINT = 0x0,
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BR_NONTAKEN_HINT = 0x2,
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BR_TAKEN_HINT = 0x3,
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BR_HINT_MASK = 0X3
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};
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/// Invert the specified predicate. != -> ==, < -> >=.
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Predicate InvertPredicate(Predicate Opcode);
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/// Assume the condition register is set by MI(a,b), return the predicate if
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/// we modify the instructions such that condition register is set by MI(b,a).
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Predicate getSwappedPredicate(Predicate Opcode);
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/// Return the condition without hint bits.
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inline unsigned getPredicateCondition(Predicate Opcode) {
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return (unsigned)(Opcode & ~BR_HINT_MASK);
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}
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/// Return the hint bits of the predicate.
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inline unsigned getPredicateHint(Predicate Opcode) {
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return (unsigned)(Opcode & BR_HINT_MASK);
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}
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/// Return predicate consisting of specified condition and hint bits.
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inline Predicate getPredicate(unsigned Condition, unsigned Hint) {
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return (Predicate)((Condition & ~BR_HINT_MASK) |
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(Hint & BR_HINT_MASK));
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}
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}
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}
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#endif
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