e63455d5e0
On some architectures such as Arm and X86 the encoding for a nop may change depending on the subtarget in operation at the time of encoding. This change replaces the per module MCSubtargetInfo retained by the targets AsmBackend in favour of passing through the local MCSubtargetInfo in operation at the time. On Arm using the architectural NOP instruction can have a performance benefit on some implementations. For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo to limit the chances of this causing problems in the future. I've not done this for other targets such as X86 as there is more frequent use of the MCSubtargetInfo and it looks to be for stable properties that we would not expect to vary per function. This change required threading STI through MCNopsFragment and MCBoundaryAlignFragment. I've attempted to take into account the in tree experimental backends. Differential Revision: https://reviews.llvm.org/D45962
282 lines
9.7 KiB
C++
282 lines
9.7 KiB
C++
//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCFixupKinds.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/BinaryFormat/MachO.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case PPC::fixup_ppc_nofixup:
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return Value;
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case PPC::fixup_ppc_brcond14:
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case PPC::fixup_ppc_brcond14abs:
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return Value & 0xfffc;
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case PPC::fixup_ppc_br24:
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case PPC::fixup_ppc_br24abs:
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case PPC::fixup_ppc_br24_notoc:
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return Value & 0x3fffffc;
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case PPC::fixup_ppc_half16:
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return Value & 0xffff;
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case PPC::fixup_ppc_half16ds:
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return Value & 0xfffc;
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case PPC::fixup_ppc_pcrel34:
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case PPC::fixup_ppc_imm34:
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return Value & 0x3ffffffff;
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}
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}
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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return 1;
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case FK_Data_2:
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case PPC::fixup_ppc_half16:
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case PPC::fixup_ppc_half16ds:
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return 2;
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case FK_Data_4:
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case PPC::fixup_ppc_brcond14:
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case PPC::fixup_ppc_brcond14abs:
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case PPC::fixup_ppc_br24:
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case PPC::fixup_ppc_br24abs:
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case PPC::fixup_ppc_br24_notoc:
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return 4;
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case PPC::fixup_ppc_pcrel34:
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case PPC::fixup_ppc_imm34:
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case FK_Data_8:
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return 8;
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case PPC::fixup_ppc_nofixup:
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return 0;
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}
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}
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namespace {
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class PPCAsmBackend : public MCAsmBackend {
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protected:
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Triple TT;
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public:
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PPCAsmBackend(const Target &T, const Triple &TT)
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: MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
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TT(TT) {}
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unsigned getNumFixupKinds() const override {
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return PPC::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_br24abs", 6, 24, 0 },
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{ "fixup_ppc_brcond14abs", 16, 14, 0 },
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{ "fixup_ppc_half16", 0, 16, 0 },
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{ "fixup_ppc_half16ds", 0, 14, 0 },
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{ "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_imm34", 0, 34, 0 },
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{ "fixup_ppc_nofixup", 0, 0, 0 }
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};
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const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
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// name offset bits flags
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{ "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_br24abs", 2, 24, 0 },
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{ "fixup_ppc_brcond14abs", 2, 14, 0 },
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{ "fixup_ppc_half16", 0, 16, 0 },
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{ "fixup_ppc_half16ds", 2, 14, 0 },
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{ "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_imm34", 0, 34, 0 },
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{ "fixup_ppc_nofixup", 0, 0, 0 }
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};
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// Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
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// do not require any extra processing.
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if (Kind >= FirstLiteralRelocationKind)
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return MCAsmBackend::getFixupKindInfo(FK_NONE);
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return (Endian == support::little
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? InfosLE
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: InfosBE)[Kind - FirstTargetFixupKind];
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}
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override {
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MCFixupKind Kind = Fixup.getKind();
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if (Kind >= FirstLiteralRelocationKind)
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return;
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Value = adjustFixupValue(Kind, Value);
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if (!Value) return; // Doesn't change encoding.
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unsigned Offset = Fixup.getOffset();
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unsigned NumBytes = getFixupKindNumBytes(Kind);
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// For each byte of the fragment that the fixup touches, mask in the bits
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// from the fixup value. The Value has been "split up" into the appropriate
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// bitfields above.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i);
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Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
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}
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}
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target) override {
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MCFixupKind Kind = Fixup.getKind();
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switch ((unsigned)Kind) {
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default:
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return Kind >= FirstLiteralRelocationKind;
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case PPC::fixup_ppc_br24:
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case PPC::fixup_ppc_br24abs:
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case PPC::fixup_ppc_br24_notoc:
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// If the target symbol has a local entry point we must not attempt
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// to resolve the fixup directly. Emit a relocation and leave
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// resolution of the final target address to the linker.
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if (const MCSymbolRefExpr *A = Target.getSymA()) {
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if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
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// The "other" values are stored in the last 6 bits of the second
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// byte. The traditional defines for STO values assume the full byte
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// and thus the shift to pack it.
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unsigned Other = S->getOther() << 2;
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if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0)
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return true;
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}
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}
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return false;
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}
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}
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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// FIXME.
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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void relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const override {
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// FIXME.
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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bool writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const override {
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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support::endian::write<uint32_t>(OS, 0x60000000, Endian);
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OS.write_zeros(Count % 4);
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return true;
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}
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};
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} // end anonymous namespace
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// FIXME: This should be in a separate file.
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namespace {
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class ELFPPCAsmBackend : public PPCAsmBackend {
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public:
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ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {}
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
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bool Is64 = TT.isPPC64();
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return createPPCELFObjectWriter(Is64, OSABI);
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}
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Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
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};
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class XCOFFPPCAsmBackend : public PPCAsmBackend {
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public:
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XCOFFPPCAsmBackend(const Target &T, const Triple &TT)
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: PPCAsmBackend(T, TT) {}
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override {
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return createPPCXCOFFObjectWriter(TT.isArch64Bit());
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}
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};
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} // end anonymous namespace
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Optional<MCFixupKind> ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
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if (TT.isOSBinFormatELF()) {
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unsigned Type;
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if (TT.isPPC64()) {
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Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
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#undef ELF_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_PPC64_NONE)
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.Case("BFD_RELOC_16", ELF::R_PPC64_ADDR16)
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.Case("BFD_RELOC_32", ELF::R_PPC64_ADDR32)
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.Case("BFD_RELOC_64", ELF::R_PPC64_ADDR64)
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.Default(-1u);
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} else {
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Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
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#undef ELF_RELOC
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.Case("BFD_RELOC_NONE", ELF::R_PPC_NONE)
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.Case("BFD_RELOC_16", ELF::R_PPC_ADDR16)
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.Case("BFD_RELOC_32", ELF::R_PPC_ADDR32)
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.Default(-1u);
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}
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if (Type != -1u)
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return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
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}
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return None;
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}
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MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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const Triple &TT = STI.getTargetTriple();
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if (TT.isOSBinFormatXCOFF())
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return new XCOFFPPCAsmBackend(T, TT);
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return new ELFPPCAsmBackend(T, TT);
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}
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