sstwcw b3e80d8ed2 [clang-format] Add space in Verilog tagged unions (#71354) ...

In a tagged union expression, there should be a space between the field
name and the data. Previously, the tag could be recognized as part of a
dotted identifier or a struct literal, and the space would be omitted.

2023-12-02 19:26:07 +00:00

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