330fa7d2a4
Given a list of constraints for InlineAsm (ex. "imr") I'm looking to modify the order in which they are chosen. Before doing so, I noticed a fair amount of logic is duplicated between SelectionDAGISel and GlobalISel for this. That is because SelectionDAGISel is also trying to lower immediates during selection. If we detangle these concerns into: 1. choose the preferred constraint 2. attempt to lower that constraint Then we can slide down the list of constraints until we find one that can be lowered. That allows the implementation to be shared between instruction selection frameworks. This makes it so that later I might only need to adjust the priority of constraints in one place, and have both selectors behave the same.
632 lines
23 KiB
C++
632 lines
23 KiB
C++
//===-- lib/CodeGen/GlobalISel/InlineAsmLowering.cpp ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering from LLVM IR inline asm to MIR INLINEASM
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/Module.h"
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#define DEBUG_TYPE "inline-asm-lowering"
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using namespace llvm;
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void InlineAsmLowering::anchor() {}
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namespace {
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/// GISelAsmOperandInfo - This contains information for each constraint that we
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/// are lowering.
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class GISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
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public:
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/// Regs - If this is a register or register class operand, this
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/// contains the set of assigned registers corresponding to the operand.
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SmallVector<Register, 1> Regs;
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explicit GISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &Info)
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: TargetLowering::AsmOperandInfo(Info) {}
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};
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using GISelAsmOperandInfoVector = SmallVector<GISelAsmOperandInfo, 16>;
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class ExtraFlags {
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unsigned Flags = 0;
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public:
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explicit ExtraFlags(const CallBase &CB) {
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const InlineAsm *IA = cast<InlineAsm>(CB.getCalledOperand());
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if (IA->hasSideEffects())
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Flags |= InlineAsm::Extra_HasSideEffects;
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if (IA->isAlignStack())
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Flags |= InlineAsm::Extra_IsAlignStack;
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if (CB.isConvergent())
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Flags |= InlineAsm::Extra_IsConvergent;
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Flags |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
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}
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void update(const TargetLowering::AsmOperandInfo &OpInfo) {
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// Ideally, we would only check against memory constraints. However, the
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// meaning of an Other constraint can be target-specific and we can't easily
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// reason about it. Therefore, be conservative and set MayLoad/MayStore
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// for Other constraints as well.
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if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
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OpInfo.ConstraintType == TargetLowering::C_Other) {
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if (OpInfo.Type == InlineAsm::isInput)
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Flags |= InlineAsm::Extra_MayLoad;
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else if (OpInfo.Type == InlineAsm::isOutput)
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Flags |= InlineAsm::Extra_MayStore;
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else if (OpInfo.Type == InlineAsm::isClobber)
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Flags |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
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}
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}
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unsigned get() const { return Flags; }
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};
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} // namespace
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/// Assign virtual/physical registers for the specified register operand.
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static void getRegistersForValue(MachineFunction &MF,
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MachineIRBuilder &MIRBuilder,
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GISelAsmOperandInfo &OpInfo,
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GISelAsmOperandInfo &RefOpInfo) {
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const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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// No work to do for memory operations.
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if (OpInfo.ConstraintType == TargetLowering::C_Memory)
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return;
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// If this is a constraint for a single physreg, or a constraint for a
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// register class, find it.
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Register AssignedReg;
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const TargetRegisterClass *RC;
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std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
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&TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
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// RC is unset only on failure. Return immediately.
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if (!RC)
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return;
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// No need to allocate a matching input constraint since the constraint it's
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// matching to has already been allocated.
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if (OpInfo.isMatchingInputConstraint())
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return;
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// Initialize NumRegs.
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unsigned NumRegs = 1;
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if (OpInfo.ConstraintVT != MVT::Other)
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NumRegs =
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TLI.getNumRegisters(MF.getFunction().getContext(), OpInfo.ConstraintVT);
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// If this is a constraint for a specific physical register, but the type of
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// the operand requires more than one register to be passed, we allocate the
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// required amount of physical registers, starting from the selected physical
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// register.
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// For this, first retrieve a register iterator for the given register class
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TargetRegisterClass::iterator I = RC->begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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// Advance the iterator to the assigned register (if set)
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if (AssignedReg) {
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for (; *I != AssignedReg; ++I)
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assert(I != RC->end() && "AssignedReg should be a member of provided RC");
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}
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// Finally, assign the registers. If the AssignedReg isn't set, create virtual
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// registers with the provided register class
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for (; NumRegs; --NumRegs, ++I) {
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assert(I != RC->end() && "Ran out of registers to allocate!");
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Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
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OpInfo.Regs.push_back(R);
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}
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}
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static void computeConstraintToUse(const TargetLowering *TLI,
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TargetLowering::AsmOperandInfo &OpInfo) {
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assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
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// Single-letter constraints ('r') are very common.
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if (OpInfo.Codes.size() == 1) {
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OpInfo.ConstraintCode = OpInfo.Codes[0];
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OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode);
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} else {
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TargetLowering::ConstraintGroup G = TLI->getConstraintPreferences(OpInfo);
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if (G.empty())
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return;
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// FIXME: prefer immediate constraints if the target allows it
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unsigned BestIdx = 0;
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for (const unsigned E = G.size();
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BestIdx < E && (G[BestIdx].second == TargetLowering::C_Other ||
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G[BestIdx].second == TargetLowering::C_Immediate);
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++BestIdx)
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;
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OpInfo.ConstraintCode = G[BestIdx].first;
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OpInfo.ConstraintType = G[BestIdx].second;
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}
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// 'X' matches anything.
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if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
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// Labels and constants are handled elsewhere ('X' is the only thing
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// that matches labels). For Functions, the type here is the type of
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// the result, which is not what we want to look at; leave them alone.
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Value *Val = OpInfo.CallOperandVal;
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if (isa<BasicBlock>(Val) || isa<ConstantInt>(Val) || isa<Function>(Val))
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return;
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// Otherwise, try to resolve it to something we know about by looking at
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// the actual operand type.
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if (const char *Repl = TLI->LowerXConstraint(OpInfo.ConstraintVT)) {
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OpInfo.ConstraintCode = Repl;
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OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode);
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}
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}
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}
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static unsigned getNumOpRegs(const MachineInstr &I, unsigned OpIdx) {
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const InlineAsm::Flag F(I.getOperand(OpIdx).getImm());
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return F.getNumOperandRegisters();
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}
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static bool buildAnyextOrCopy(Register Dst, Register Src,
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MachineIRBuilder &MIRBuilder) {
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const TargetRegisterInfo *TRI =
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MIRBuilder.getMF().getSubtarget().getRegisterInfo();
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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auto SrcTy = MRI->getType(Src);
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if (!SrcTy.isValid()) {
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LLVM_DEBUG(dbgs() << "Source type for copy is not valid\n");
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return false;
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}
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unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI);
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unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI);
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if (DstSize < SrcSize) {
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LLVM_DEBUG(dbgs() << "Input can't fit in destination reg class\n");
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return false;
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}
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// Attempt to anyext small scalar sources.
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if (DstSize > SrcSize) {
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if (!SrcTy.isScalar()) {
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LLVM_DEBUG(dbgs() << "Can't extend non-scalar input to size of"
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"destination register class\n");
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return false;
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}
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Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0);
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}
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MIRBuilder.buildCopy(Dst, Src);
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return true;
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}
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bool InlineAsmLowering::lowerInlineAsm(
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MachineIRBuilder &MIRBuilder, const CallBase &Call,
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std::function<ArrayRef<Register>(const Value &Val)> GetOrCreateVRegs)
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const {
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const InlineAsm *IA = cast<InlineAsm>(Call.getCalledOperand());
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/// ConstraintOperands - Information about all of the constraints.
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GISelAsmOperandInfoVector ConstraintOperands;
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = F.getParent()->getDataLayout();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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MachineRegisterInfo *MRI = MIRBuilder.getMRI();
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TargetLowering::AsmOperandInfoVector TargetConstraints =
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TLI->ParseConstraints(DL, TRI, Call);
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ExtraFlags ExtraInfo(Call);
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unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
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unsigned ResNo = 0; // ResNo - The result number of the next output.
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for (auto &T : TargetConstraints) {
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ConstraintOperands.push_back(GISelAsmOperandInfo(T));
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GISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
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// Compute the value type for each operand.
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if (OpInfo.hasArg()) {
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OpInfo.CallOperandVal = const_cast<Value *>(Call.getArgOperand(ArgNo));
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if (isa<BasicBlock>(OpInfo.CallOperandVal)) {
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LLVM_DEBUG(dbgs() << "Basic block input operands not supported yet\n");
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return false;
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}
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Type *OpTy = OpInfo.CallOperandVal->getType();
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// If this is an indirect operand, the operand is a pointer to the
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// accessed type.
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if (OpInfo.isIndirect) {
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OpTy = Call.getParamElementType(ArgNo);
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assert(OpTy && "Indirect operand must have elementtype attribute");
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}
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// FIXME: Support aggregate input operands
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if (!OpTy->isSingleValueType()) {
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LLVM_DEBUG(
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dbgs() << "Aggregate input operands are not supported yet\n");
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return false;
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}
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OpInfo.ConstraintVT =
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TLI->getAsmOperandValueType(DL, OpTy, true).getSimpleVT();
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++ArgNo;
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} else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
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assert(!Call.getType()->isVoidTy() && "Bad inline asm!");
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if (StructType *STy = dyn_cast<StructType>(Call.getType())) {
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OpInfo.ConstraintVT =
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TLI->getSimpleValueType(DL, STy->getElementType(ResNo));
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} else {
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assert(ResNo == 0 && "Asm only has one result!");
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OpInfo.ConstraintVT =
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TLI->getAsmOperandValueType(DL, Call.getType()).getSimpleVT();
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}
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++ResNo;
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} else {
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assert(OpInfo.Type != InlineAsm::isLabel &&
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"GlobalISel currently doesn't support callbr");
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OpInfo.ConstraintVT = MVT::Other;
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}
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if (OpInfo.ConstraintVT == MVT::i64x8)
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return false;
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// Compute the constraint code and ConstraintType to use.
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computeConstraintToUse(TLI, OpInfo);
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// The selected constraint type might expose new sideeffects
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ExtraInfo.update(OpInfo);
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}
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// At this point, all operand types are decided.
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// Create the MachineInstr, but don't insert it yet since input
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// operands still need to insert instructions before this one
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auto Inst = MIRBuilder.buildInstrNoInsert(TargetOpcode::INLINEASM)
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.addExternalSymbol(IA->getAsmString().c_str())
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.addImm(ExtraInfo.get());
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// Starting from this operand: flag followed by register(s) will be added as
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// operands to Inst for each constraint. Used for matching input constraints.
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unsigned StartIdx = Inst->getNumOperands();
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// Collects the output operands for later processing
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GISelAsmOperandInfoVector OutputOperands;
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for (auto &OpInfo : ConstraintOperands) {
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GISelAsmOperandInfo &RefOpInfo =
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OpInfo.isMatchingInputConstraint()
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? ConstraintOperands[OpInfo.getMatchedOperand()]
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: OpInfo;
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// Assign registers for register operands
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getRegistersForValue(MF, MIRBuilder, OpInfo, RefOpInfo);
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switch (OpInfo.Type) {
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case InlineAsm::isOutput:
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if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
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const InlineAsm::ConstraintCode ConstraintID =
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TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
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assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
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"Failed to convert memory constraint code to constraint id.");
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// Add information to the INLINEASM instruction to know about this
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// output.
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InlineAsm::Flag Flag(InlineAsm::Kind::Mem, 1);
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Flag.setMemConstraint(ConstraintID);
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Inst.addImm(Flag);
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ArrayRef<Register> SourceRegs =
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GetOrCreateVRegs(*OpInfo.CallOperandVal);
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assert(
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SourceRegs.size() == 1 &&
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"Expected the memory output to fit into a single virtual register");
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Inst.addReg(SourceRegs[0]);
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} else {
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// Otherwise, this outputs to a register (directly for C_Register /
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// C_RegisterClass/C_Other.
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assert(OpInfo.ConstraintType == TargetLowering::C_Register ||
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OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
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OpInfo.ConstraintType == TargetLowering::C_Other);
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// Find a register that we can use.
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if (OpInfo.Regs.empty()) {
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LLVM_DEBUG(dbgs()
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<< "Couldn't allocate output register for constraint\n");
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return false;
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}
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// Add information to the INLINEASM instruction to know that this
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// register is set.
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InlineAsm::Flag Flag(OpInfo.isEarlyClobber
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? InlineAsm::Kind::RegDefEarlyClobber
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: InlineAsm::Kind::RegDef,
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OpInfo.Regs.size());
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if (OpInfo.Regs.front().isVirtual()) {
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// Put the register class of the virtual registers in the flag word.
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// That way, later passes can recompute register class constraints for
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// inline assembly as well as normal instructions. Don't do this for
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// tied operands that can use the regclass information from the def.
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const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
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Flag.setRegClass(RC->getID());
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}
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Inst.addImm(Flag);
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for (Register Reg : OpInfo.Regs) {
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Inst.addReg(Reg,
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RegState::Define | getImplRegState(Reg.isPhysical()) |
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(OpInfo.isEarlyClobber ? RegState::EarlyClobber : 0));
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}
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// Remember this output operand for later processing
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OutputOperands.push_back(OpInfo);
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}
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break;
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case InlineAsm::isInput:
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case InlineAsm::isLabel: {
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if (OpInfo.isMatchingInputConstraint()) {
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unsigned DefIdx = OpInfo.getMatchedOperand();
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// Find operand with register def that corresponds to DefIdx.
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unsigned InstFlagIdx = StartIdx;
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for (unsigned i = 0; i < DefIdx; ++i)
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InstFlagIdx += getNumOpRegs(*Inst, InstFlagIdx) + 1;
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assert(getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag");
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const InlineAsm::Flag MatchedOperandFlag(Inst->getOperand(InstFlagIdx).getImm());
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if (MatchedOperandFlag.isMemKind()) {
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LLVM_DEBUG(dbgs() << "Matching input constraint to mem operand not "
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"supported. This should be target specific.\n");
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return false;
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}
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if (!MatchedOperandFlag.isRegDefKind() && !MatchedOperandFlag.isRegDefEarlyClobberKind()) {
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LLVM_DEBUG(dbgs() << "Unknown matching constraint\n");
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return false;
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}
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// We want to tie input to register in next operand.
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unsigned DefRegIdx = InstFlagIdx + 1;
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Register Def = Inst->getOperand(DefRegIdx).getReg();
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ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
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assert(SrcRegs.size() == 1 && "Single register is expected here");
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// When Def is physreg: use given input.
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Register In = SrcRegs[0];
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// When Def is vreg: copy input to new vreg with same reg class as Def.
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if (Def.isVirtual()) {
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In = MRI->createVirtualRegister(MRI->getRegClass(Def));
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if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder))
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return false;
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}
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// Add Flag and input register operand (In) to Inst. Tie In to Def.
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InlineAsm::Flag UseFlag(InlineAsm::Kind::RegUse, 1);
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UseFlag.setMatchingOp(DefIdx);
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Inst.addImm(UseFlag);
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Inst.addReg(In);
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Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1);
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break;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Other &&
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OpInfo.isIndirect) {
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LLVM_DEBUG(dbgs() << "Indirect input operands with unknown constraint "
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"not supported yet\n");
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return false;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
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OpInfo.ConstraintType == TargetLowering::C_Other) {
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std::vector<MachineOperand> Ops;
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if (!lowerAsmOperandForConstraint(OpInfo.CallOperandVal,
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OpInfo.ConstraintCode, Ops,
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MIRBuilder)) {
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LLVM_DEBUG(dbgs() << "Don't support constraint: "
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<< OpInfo.ConstraintCode << " yet\n");
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return false;
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}
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assert(Ops.size() > 0 &&
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"Expected constraint to be lowered to at least one operand");
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// Add information to the INLINEASM node to know about this input.
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const unsigned OpFlags =
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InlineAsm::Flag(InlineAsm::Kind::Imm, Ops.size());
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Inst.addImm(OpFlags);
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Inst.add(Ops);
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break;
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}
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if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
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if (!OpInfo.isIndirect) {
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LLVM_DEBUG(dbgs()
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<< "Cannot indirectify memory input operands yet\n");
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return false;
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}
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assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
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const InlineAsm::ConstraintCode ConstraintID =
|
|
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
|
|
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
|
|
OpFlags.setMemConstraint(ConstraintID);
|
|
Inst.addImm(OpFlags);
|
|
ArrayRef<Register> SourceRegs =
|
|
GetOrCreateVRegs(*OpInfo.CallOperandVal);
|
|
assert(
|
|
SourceRegs.size() == 1 &&
|
|
"Expected the memory input to fit into a single virtual register");
|
|
Inst.addReg(SourceRegs[0]);
|
|
break;
|
|
}
|
|
|
|
assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
|
|
OpInfo.ConstraintType == TargetLowering::C_Register) &&
|
|
"Unknown constraint type!");
|
|
|
|
if (OpInfo.isIndirect) {
|
|
LLVM_DEBUG(dbgs() << "Can't handle indirect register inputs yet "
|
|
"for constraint '"
|
|
<< OpInfo.ConstraintCode << "'\n");
|
|
return false;
|
|
}
|
|
|
|
// Copy the input into the appropriate registers.
|
|
if (OpInfo.Regs.empty()) {
|
|
LLVM_DEBUG(
|
|
dbgs()
|
|
<< "Couldn't allocate input register for register constraint\n");
|
|
return false;
|
|
}
|
|
|
|
unsigned NumRegs = OpInfo.Regs.size();
|
|
ArrayRef<Register> SourceRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
|
|
assert(NumRegs == SourceRegs.size() &&
|
|
"Expected the number of input registers to match the number of "
|
|
"source registers");
|
|
|
|
if (NumRegs > 1) {
|
|
LLVM_DEBUG(dbgs() << "Input operands with multiple input registers are "
|
|
"not supported yet\n");
|
|
return false;
|
|
}
|
|
|
|
InlineAsm::Flag Flag(InlineAsm::Kind::RegUse, NumRegs);
|
|
if (OpInfo.Regs.front().isVirtual()) {
|
|
// Put the register class of the virtual registers in the flag word.
|
|
const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
|
|
Flag.setRegClass(RC->getID());
|
|
}
|
|
Inst.addImm(Flag);
|
|
if (!buildAnyextOrCopy(OpInfo.Regs[0], SourceRegs[0], MIRBuilder))
|
|
return false;
|
|
Inst.addReg(OpInfo.Regs[0]);
|
|
break;
|
|
}
|
|
|
|
case InlineAsm::isClobber: {
|
|
|
|
const unsigned NumRegs = OpInfo.Regs.size();
|
|
if (NumRegs > 0) {
|
|
unsigned Flag = InlineAsm::Flag(InlineAsm::Kind::Clobber, NumRegs);
|
|
Inst.addImm(Flag);
|
|
|
|
for (Register Reg : OpInfo.Regs) {
|
|
Inst.addReg(Reg, RegState::Define | RegState::EarlyClobber |
|
|
getImplRegState(Reg.isPhysical()));
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (const MDNode *SrcLoc = Call.getMetadata("srcloc"))
|
|
Inst.addMetadata(SrcLoc);
|
|
|
|
// All inputs are handled, insert the instruction now
|
|
MIRBuilder.insertInstr(Inst);
|
|
|
|
// Finally, copy the output operands into the output registers
|
|
ArrayRef<Register> ResRegs = GetOrCreateVRegs(Call);
|
|
if (ResRegs.size() != OutputOperands.size()) {
|
|
LLVM_DEBUG(dbgs() << "Expected the number of output registers to match the "
|
|
"number of destination registers\n");
|
|
return false;
|
|
}
|
|
for (unsigned int i = 0, e = ResRegs.size(); i < e; i++) {
|
|
GISelAsmOperandInfo &OpInfo = OutputOperands[i];
|
|
|
|
if (OpInfo.Regs.empty())
|
|
continue;
|
|
|
|
switch (OpInfo.ConstraintType) {
|
|
case TargetLowering::C_Register:
|
|
case TargetLowering::C_RegisterClass: {
|
|
if (OpInfo.Regs.size() > 1) {
|
|
LLVM_DEBUG(dbgs() << "Output operands with multiple defining "
|
|
"registers are not supported yet\n");
|
|
return false;
|
|
}
|
|
|
|
Register SrcReg = OpInfo.Regs[0];
|
|
unsigned SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
|
|
LLT ResTy = MRI->getType(ResRegs[i]);
|
|
if (ResTy.isScalar() && ResTy.getSizeInBits() < SrcSize) {
|
|
// First copy the non-typed virtual register into a generic virtual
|
|
// register
|
|
Register Tmp1Reg =
|
|
MRI->createGenericVirtualRegister(LLT::scalar(SrcSize));
|
|
MIRBuilder.buildCopy(Tmp1Reg, SrcReg);
|
|
// Need to truncate the result of the register
|
|
MIRBuilder.buildTrunc(ResRegs[i], Tmp1Reg);
|
|
} else if (ResTy.getSizeInBits() == SrcSize) {
|
|
MIRBuilder.buildCopy(ResRegs[i], SrcReg);
|
|
} else {
|
|
LLVM_DEBUG(dbgs() << "Unhandled output operand with "
|
|
"mismatched register size\n");
|
|
return false;
|
|
}
|
|
|
|
break;
|
|
}
|
|
case TargetLowering::C_Immediate:
|
|
case TargetLowering::C_Other:
|
|
LLVM_DEBUG(
|
|
dbgs() << "Cannot lower target specific output constraints yet\n");
|
|
return false;
|
|
case TargetLowering::C_Memory:
|
|
break; // Already handled.
|
|
case TargetLowering::C_Address:
|
|
break; // Silence warning.
|
|
case TargetLowering::C_Unknown:
|
|
LLVM_DEBUG(dbgs() << "Unexpected unknown constraint\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool InlineAsmLowering::lowerAsmOperandForConstraint(
|
|
Value *Val, StringRef Constraint, std::vector<MachineOperand> &Ops,
|
|
MachineIRBuilder &MIRBuilder) const {
|
|
if (Constraint.size() > 1)
|
|
return false;
|
|
|
|
char ConstraintLetter = Constraint[0];
|
|
switch (ConstraintLetter) {
|
|
default:
|
|
return false;
|
|
case 'i': // Simple Integer or Relocatable Constant
|
|
case 'n': // immediate integer with a known value.
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
|
|
assert(CI->getBitWidth() <= 64 &&
|
|
"expected immediate to fit into 64-bits");
|
|
// Boolean constants should be zero-extended, others are sign-extended
|
|
bool IsBool = CI->getBitWidth() == 1;
|
|
int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue();
|
|
Ops.push_back(MachineOperand::CreateImm(ExtVal));
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
}
|