3c5b42acd3
Previously we allocated one object for each GPR. We also allocated the same offset twice, once to save for VASTART and then again for the first register in the save loop. This patch uses a single object for all the registers and shares this with VASTART. This is more consistent with other targets like AArch64 and ARM. I've removed the setValue(nullptr) from the memory operand now. Having a single object makes me a lot more comfortable about alias analysis being able to see what is going on. This led to the scheduling changes in push-pop-popret.ll and vararg.ll.
632 lines
24 KiB
C++
632 lines
24 KiB
C++
//===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVCallLowering.h"
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#include "RISCVISelLowering.h"
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#include "RISCVMachineFunctionInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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using namespace llvm;
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namespace {
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struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
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private:
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// The function used internally to assign args - we ignore the AssignFn stored
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// by OutgoingValueAssigner since RISC-V implements its CC using a custom
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// function with a different signature.
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RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn;
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// Whether this is assigning args for a return.
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bool IsRet;
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public:
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RISCVOutgoingValueAssigner(
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RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
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: CallLowering::OutgoingValueAssigner(nullptr),
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RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
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bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
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CCState &State) override {
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MachineFunction &MF = State.getMachineFunction();
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const DataLayout &DL = MF.getDataLayout();
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const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
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if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
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LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
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*Subtarget.getTargetLowering(),
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/*FirstMaskArgument=*/std::nullopt))
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return true;
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StackSize = State.getStackSize();
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return false;
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}
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};
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struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
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RISCVOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB)
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: OutgoingValueHandler(B, MRI), MIB(MIB),
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Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {}
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Register getStackAddress(uint64_t MemSize, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) override {
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MachineFunction &MF = MIRBuilder.getMF();
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LLT p0 = LLT::pointer(0, Subtarget.getXLen());
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LLT sXLen = LLT::scalar(Subtarget.getXLen());
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if (!SPReg)
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SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0);
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auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset);
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auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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MPO = MachinePointerInfo::getStack(MF, Offset);
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return AddrReg.getReg(0);
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}
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void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
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const MachinePointerInfo &MPO,
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const CCValAssign &VA) override {
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MachineFunction &MF = MIRBuilder.getMF();
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uint64_t LocMemOffset = VA.getLocMemOffset();
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// TODO: Move StackAlignment to subtarget and share with FrameLowering.
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auto MMO =
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MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
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commonAlignment(Align(16), LocMemOffset));
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildStore(ExtReg, Addr, *MMO);
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}
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void assignValueToReg(Register ValVReg, Register PhysReg,
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const CCValAssign &VA) override {
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// If we're passing an f32 value into an i64, anyextend before copying.
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if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32)
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ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(64), ValVReg).getReg(0);
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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}
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unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs,
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std::function<void()> *Thunk) override {
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assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
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const CCValAssign &VALo = VAs[0];
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const CCValAssign &VAHi = VAs[1];
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assert(VAHi.needsCustom() && "Value doesn't need custom handling");
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assert(VALo.getValNo() == VAHi.getValNo() &&
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"Values belong to different arguments");
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assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
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VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
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"unexpected custom value");
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Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
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MRI.createGenericVirtualRegister(LLT::scalar(32))};
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MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
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if (VAHi.isMemLoc()) {
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LLT MemTy(VAHi.getLocVT());
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MachinePointerInfo MPO;
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Register StackAddr = getStackAddress(
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MemTy.getSizeInBytes(), VAHi.getLocMemOffset(), MPO, Arg.Flags[0]);
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assignValueToAddress(NewRegs[1], StackAddr, MemTy, MPO,
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const_cast<CCValAssign &>(VAHi));
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}
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auto assignFunc = [=]() {
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assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo);
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if (VAHi.isRegLoc())
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assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);
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};
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if (Thunk) {
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*Thunk = assignFunc;
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return 1;
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}
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assignFunc();
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return 1;
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}
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private:
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MachineInstrBuilder MIB;
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// Cache the SP register vreg if we need it more than once in this call site.
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Register SPReg;
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const RISCVSubtarget &Subtarget;
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};
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struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
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private:
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// The function used internally to assign args - we ignore the AssignFn stored
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// by IncomingValueAssigner since RISC-V implements its CC using a custom
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// function with a different signature.
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RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn;
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// Whether this is assigning args from a return.
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bool IsRet;
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public:
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RISCVIncomingValueAssigner(
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RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
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: CallLowering::IncomingValueAssigner(nullptr),
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RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
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bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
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CCState &State) override {
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MachineFunction &MF = State.getMachineFunction();
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const DataLayout &DL = MF.getDataLayout();
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const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
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if (LocVT.isScalableVector())
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MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
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if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
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LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
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*Subtarget.getTargetLowering(),
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/*FirstMaskArgument=*/std::nullopt))
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return true;
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StackSize = State.getStackSize();
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return false;
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}
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};
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struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
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RISCVIncomingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
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: IncomingValueHandler(B, MRI),
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Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {}
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Register getStackAddress(uint64_t MemSize, int64_t Offset,
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MachinePointerInfo &MPO,
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ISD::ArgFlagsTy Flags) override {
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MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo();
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int FI = MFI.CreateFixedObject(MemSize, Offset, /*Immutable=*/true);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI)
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.getReg(0);
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}
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void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
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const MachinePointerInfo &MPO,
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const CCValAssign &VA) override {
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MachineFunction &MF = MIRBuilder.getMF();
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auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
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inferAlignFromPtrInfo(MF, MPO));
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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}
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void assignValueToReg(Register ValVReg, Register PhysReg,
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const CCValAssign &VA) override {
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markPhysRegUsed(PhysReg);
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IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
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}
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unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs,
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std::function<void()> *Thunk) override {
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assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
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const CCValAssign &VALo = VAs[0];
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const CCValAssign &VAHi = VAs[1];
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assert(VAHi.needsCustom() && "Value doesn't need custom handling");
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assert(VALo.getValNo() == VAHi.getValNo() &&
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"Values belong to different arguments");
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assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
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VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
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"unexpected custom value");
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Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
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MRI.createGenericVirtualRegister(LLT::scalar(32))};
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if (VAHi.isMemLoc()) {
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LLT MemTy(VAHi.getLocVT());
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MachinePointerInfo MPO;
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Register StackAddr = getStackAddress(
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MemTy.getSizeInBytes(), VAHi.getLocMemOffset(), MPO, Arg.Flags[0]);
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assignValueToAddress(NewRegs[1], StackAddr, MemTy, MPO,
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const_cast<CCValAssign &>(VAHi));
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}
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assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo);
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if (VAHi.isRegLoc())
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assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);
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MIRBuilder.buildMergeLikeInstr(Arg.Regs[0], NewRegs);
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return 1;
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}
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/// How the physical register gets marked varies between formal
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/// parameters (it's a basic-block live-in), and a call instruction
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/// (it's an implicit-def of the BL).
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virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
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private:
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const RISCVSubtarget &Subtarget;
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};
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struct RISCVFormalArgHandler : public RISCVIncomingValueHandler {
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RISCVFormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
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: RISCVIncomingValueHandler(B, MRI) {}
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void markPhysRegUsed(MCRegister PhysReg) override {
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MIRBuilder.getMRI()->addLiveIn(PhysReg);
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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};
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struct RISCVCallReturnHandler : public RISCVIncomingValueHandler {
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RISCVCallReturnHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: RISCVIncomingValueHandler(B, MRI), MIB(MIB) {}
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void markPhysRegUsed(MCRegister PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder MIB;
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};
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} // namespace
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RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
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: CallLowering(&TLI) {}
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/// Return true if scalable vector with ScalarTy is legal for lowering.
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static bool isLegalElementTypeForRVV(Type *EltTy,
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const RISCVSubtarget &Subtarget) {
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if (EltTy->isPointerTy())
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return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
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if (EltTy->isIntegerTy(1) || EltTy->isIntegerTy(8) ||
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EltTy->isIntegerTy(16) || EltTy->isIntegerTy(32))
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return true;
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if (EltTy->isIntegerTy(64))
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return Subtarget.hasVInstructionsI64();
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if (EltTy->isHalfTy())
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return Subtarget.hasVInstructionsF16();
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if (EltTy->isBFloatTy())
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return Subtarget.hasVInstructionsBF16();
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if (EltTy->isFloatTy())
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return Subtarget.hasVInstructionsF32();
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if (EltTy->isDoubleTy())
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return Subtarget.hasVInstructionsF64();
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return false;
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}
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// TODO: Support all argument types.
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// TODO: Remove IsLowerArgs argument by adding support for vectors in lowerCall.
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static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
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bool IsLowerArgs = false) {
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// TODO: Integers larger than 2*XLen are passed indirectly which is not
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// supported yet.
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if (T->isIntegerTy())
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return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2;
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if (T->isFloatTy() || T->isDoubleTy())
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return true;
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if (T->isPointerTy())
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return true;
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// TODO: Support fixed vector types.
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if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
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T->isScalableTy() &&
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isLegalElementTypeForRVV(T->getScalarType(), Subtarget))
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return true;
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return false;
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}
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// TODO: Only integer, pointer and aggregate types are supported now.
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// TODO: Remove IsLowerRetVal argument by adding support for vectors in
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// lowerCall.
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static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget,
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bool IsLowerRetVal = false) {
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// TODO: Integers larger than 2*XLen are passed indirectly which is not
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// supported yet.
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if (T->isIntegerTy())
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return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2;
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if (T->isFloatTy() || T->isDoubleTy())
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return true;
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if (T->isPointerTy())
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return true;
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if (T->isArrayTy())
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return isSupportedReturnType(T->getArrayElementType(), Subtarget);
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if (T->isStructTy()) {
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auto StructT = cast<StructType>(T);
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for (unsigned i = 0, e = StructT->getNumElements(); i != e; ++i)
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if (!isSupportedReturnType(StructT->getElementType(i), Subtarget))
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return false;
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return true;
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}
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if (IsLowerRetVal && T->isVectorTy() && Subtarget.hasVInstructions() &&
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T->isScalableTy() &&
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isLegalElementTypeForRVV(T->getScalarType(), Subtarget))
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return true;
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return false;
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}
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bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
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const Value *Val,
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ArrayRef<Register> VRegs,
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MachineInstrBuilder &Ret) const {
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if (!Val)
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return true;
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const RISCVSubtarget &Subtarget =
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MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
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if (!isSupportedReturnType(Val->getType(), Subtarget, /*IsLowerRetVal=*/true))
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return false;
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MachineFunction &MF = MIRBuilder.getMF();
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const DataLayout &DL = MF.getDataLayout();
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const Function &F = MF.getFunction();
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CallingConv::ID CC = F.getCallingConv();
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ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
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setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
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SmallVector<ArgInfo, 4> SplitRetInfos;
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splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
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RISCVOutgoingValueAssigner Assigner(
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CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
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/*IsRet=*/true);
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RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
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return determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
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MIRBuilder, CC, F.isVarArg());
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}
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bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI) const {
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assert(!Val == VRegs.empty() && "Return value without a vreg");
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MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
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if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
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return false;
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MIRBuilder.insertInstr(Ret);
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return true;
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}
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/// If there are varargs that were passed in a0-a7, the data in those registers
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/// must be copied to the varargs save area on the stack.
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void RISCVCallLowering::saveVarArgRegisters(
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MachineIRBuilder &MIRBuilder, CallLowering::IncomingValueHandler &Handler,
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IncomingValueAssigner &Assigner, CCState &CCInfo) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
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unsigned XLenInBytes = Subtarget.getXLen() / 8;
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ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
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MachineFrameInfo &MFI = MF.getFrameInfo();
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RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
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// Size of the vararg save area. For now, the varargs save area is either
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// zero or large enough to hold a0-a7.
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int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
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int FI;
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// If all registers are allocated, then all varargs must be passed on the
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// stack and we don't need to save any argregs.
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if (VarArgsSaveSize == 0) {
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int VaArgOffset = Assigner.StackSize;
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FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
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} else {
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int VaArgOffset = -VarArgsSaveSize;
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FI = MFI.CreateFixedObject(VarArgsSaveSize, VaArgOffset, true);
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// If saving an odd number of registers then create an extra stack slot to
|
|
// ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
|
|
// offsets to even-numbered registered remain 2*XLEN-aligned.
|
|
if (Idx % 2) {
|
|
MFI.CreateFixedObject(XLenInBytes,
|
|
VaArgOffset - static_cast<int>(XLenInBytes), true);
|
|
VarArgsSaveSize += XLenInBytes;
|
|
}
|
|
|
|
const LLT p0 = LLT::pointer(MF.getDataLayout().getAllocaAddrSpace(),
|
|
Subtarget.getXLen());
|
|
const LLT sXLen = LLT::scalar(Subtarget.getXLen());
|
|
|
|
auto FIN = MIRBuilder.buildFrameIndex(p0, FI);
|
|
auto Offset = MIRBuilder.buildConstant(
|
|
MRI.createGenericVirtualRegister(sXLen), XLenInBytes);
|
|
|
|
// Copy the integer registers that may have been used for passing varargs
|
|
// to the vararg save area.
|
|
const MVT XLenVT = Subtarget.getXLenVT();
|
|
for (unsigned I = Idx; I < ArgRegs.size(); ++I) {
|
|
const Register VReg = MRI.createGenericVirtualRegister(sXLen);
|
|
Handler.assignValueToReg(
|
|
VReg, ArgRegs[I],
|
|
CCValAssign::getReg(I + MF.getFunction().getNumOperands(), XLenVT,
|
|
ArgRegs[I], XLenVT, CCValAssign::Full));
|
|
auto MPO =
|
|
MachinePointerInfo::getFixedStack(MF, FI, (I - Idx) * XLenInBytes);
|
|
MIRBuilder.buildStore(VReg, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
|
|
FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
|
|
FIN.getReg(0), Offset);
|
|
}
|
|
}
|
|
|
|
// Record the frame index of the first variable argument which is a value
|
|
// necessary to G_VASTART.
|
|
RVFI->setVarArgsFrameIndex(FI);
|
|
RVFI->setVarArgsSaveSize(VarArgsSaveSize);
|
|
}
|
|
|
|
bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
|
|
const Function &F,
|
|
ArrayRef<ArrayRef<Register>> VRegs,
|
|
FunctionLoweringInfo &FLI) const {
|
|
// Early exit if there are no arguments. varargs are not part of F.args() but
|
|
// must be lowered.
|
|
if (F.arg_empty() && !F.isVarArg())
|
|
return true;
|
|
|
|
const RISCVSubtarget &Subtarget =
|
|
MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
|
|
for (auto &Arg : F.args()) {
|
|
if (!isSupportedArgumentType(Arg.getType(), Subtarget,
|
|
/*IsLowerArgs=*/true))
|
|
return false;
|
|
}
|
|
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const DataLayout &DL = MF.getDataLayout();
|
|
CallingConv::ID CC = F.getCallingConv();
|
|
|
|
SmallVector<ArgInfo, 32> SplitArgInfos;
|
|
unsigned Index = 0;
|
|
for (auto &Arg : F.args()) {
|
|
// Construct the ArgInfo object from destination register and argument type.
|
|
ArgInfo AInfo(VRegs[Index], Arg.getType(), Index);
|
|
setArgFlags(AInfo, Index + AttributeList::FirstArgIndex, DL, F);
|
|
|
|
// Handle any required merging from split value types from physical
|
|
// registers into the desired VReg. ArgInfo objects are constructed
|
|
// correspondingly and appended to SplitArgInfos.
|
|
splitToValueTypes(AInfo, SplitArgInfos, DL, CC);
|
|
|
|
++Index;
|
|
}
|
|
|
|
RISCVIncomingValueAssigner Assigner(
|
|
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
|
|
/*IsRet=*/false);
|
|
RISCVFormalArgHandler Handler(MIRBuilder, MF.getRegInfo());
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
|
CCState CCInfo(CC, F.isVarArg(), MIRBuilder.getMF(), ArgLocs, F.getContext());
|
|
if (!determineAssignments(Assigner, SplitArgInfos, CCInfo) ||
|
|
!handleAssignments(Handler, SplitArgInfos, CCInfo, ArgLocs, MIRBuilder))
|
|
return false;
|
|
|
|
if (F.isVarArg())
|
|
saveVarArgRegisters(MIRBuilder, Handler, Assigner, CCInfo);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
|
|
CallLoweringInfo &Info) const {
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const DataLayout &DL = MF.getDataLayout();
|
|
const Function &F = MF.getFunction();
|
|
CallingConv::ID CC = F.getCallingConv();
|
|
|
|
const RISCVSubtarget &Subtarget =
|
|
MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
|
|
for (auto &AInfo : Info.OrigArgs) {
|
|
if (!isSupportedArgumentType(AInfo.Ty, Subtarget))
|
|
return false;
|
|
}
|
|
|
|
if (!Info.OrigRet.Ty->isVoidTy() &&
|
|
!isSupportedReturnType(Info.OrigRet.Ty, Subtarget))
|
|
return false;
|
|
|
|
MachineInstrBuilder CallSeqStart =
|
|
MIRBuilder.buildInstr(RISCV::ADJCALLSTACKDOWN);
|
|
|
|
SmallVector<ArgInfo, 32> SplitArgInfos;
|
|
SmallVector<ISD::OutputArg, 8> Outs;
|
|
for (auto &AInfo : Info.OrigArgs) {
|
|
// Handle any required unmerging of split value types from a given VReg into
|
|
// physical registers. ArgInfo objects are constructed correspondingly and
|
|
// appended to SplitArgInfos.
|
|
splitToValueTypes(AInfo, SplitArgInfos, DL, CC);
|
|
}
|
|
|
|
// TODO: Support tail calls.
|
|
Info.IsTailCall = false;
|
|
|
|
// Select the recommended relocation type R_RISCV_CALL_PLT.
|
|
if (!Info.Callee.isReg())
|
|
Info.Callee.setTargetFlags(RISCVII::MO_PLT);
|
|
|
|
MachineInstrBuilder Call =
|
|
MIRBuilder
|
|
.buildInstrNoInsert(Info.Callee.isReg() ? RISCV::PseudoCALLIndirect
|
|
: RISCV::PseudoCALL)
|
|
.add(Info.Callee);
|
|
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
|
|
Call.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
|
|
|
|
RISCVOutgoingValueAssigner ArgAssigner(
|
|
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
|
|
/*IsRet=*/false);
|
|
RISCVOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), Call);
|
|
if (!determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgInfos,
|
|
MIRBuilder, CC, Info.IsVarArg))
|
|
return false;
|
|
|
|
MIRBuilder.insertInstr(Call);
|
|
|
|
CallSeqStart.addImm(ArgAssigner.StackSize).addImm(0);
|
|
MIRBuilder.buildInstr(RISCV::ADJCALLSTACKUP)
|
|
.addImm(ArgAssigner.StackSize)
|
|
.addImm(0);
|
|
|
|
// If Callee is a reg, since it is used by a target specific
|
|
// instruction, it must have a register class matching the
|
|
// constraint of that instruction.
|
|
if (Call->getOperand(0).isReg())
|
|
constrainOperandRegClass(MF, *TRI, MF.getRegInfo(),
|
|
*Subtarget.getInstrInfo(),
|
|
*Subtarget.getRegBankInfo(), *Call,
|
|
Call->getDesc(), Call->getOperand(0), 0);
|
|
|
|
if (Info.OrigRet.Ty->isVoidTy())
|
|
return true;
|
|
|
|
SmallVector<ArgInfo, 4> SplitRetInfos;
|
|
splitToValueTypes(Info.OrigRet, SplitRetInfos, DL, CC);
|
|
|
|
RISCVIncomingValueAssigner RetAssigner(
|
|
CC == CallingConv::Fast ? RISCV::CC_RISCV_FastCC : RISCV::CC_RISCV,
|
|
/*IsRet=*/true);
|
|
RISCVCallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), Call);
|
|
if (!determineAndHandleAssignments(RetHandler, RetAssigner, SplitRetInfos,
|
|
MIRBuilder, CC, Info.IsVarArg))
|
|
return false;
|
|
|
|
return true;
|
|
}
|