caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
1daf2994de49d1ecba4bee4e6842aa8a564cbc96
clang-p2996/llvm/lib/Target/RISCV
History
Wang Pengcheng f9c908862a [RISCV] Split TuneShiftedZExtFusion (#76032) 
We split `TuneShiftedZExtFusion` into three fusions to make them
reusable and match the GCC implementation[1].

The zexth/zextw fusions can be reused by XiangShan[2] and other
commercial processors, but shifted zero extension is not so common.

`macro-fusions-veyron-v1.mir` is renamed so it's not relevant to
specific processor.

References:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637303.html
[2] https://xiangshan-doc.readthedocs.io/zh_CN/latest/frontend/decode
2023-12-22 14:37:26 +08:00
..
AsmParser
[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)
2023-12-11 21:01:36 -08:00
Disassembler
[RISCV][MC] MC layer support for xcvmem and xcvelw extensions
2023-11-16 09:46:11 +08:00
GISel
[RISCV][GISEL] Fix legalization for G_MERGE/UNMERGE_VALUES (#75619)
2023-12-18 19:21:18 -05:00
MCA
[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (#69788)
2023-10-27 12:16:28 +01:00
MCTargetDesc
[RISCV] Move TargetOverlapConstraintType from RISCVVPseudo to TSFlags. NFC (#75877)
2023-12-18 22:25:34 -08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add missing component Scalar (#71905)
2023-11-10 16:43:42 +08:00
RISCV.h
[Target] Remove unused forward declarations (NFC)
2023-12-10 10:38:55 -08:00
RISCV.td
…
RISCVAsmPrinter.cpp
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (#72053)
2023-11-13 22:45:33 +08:00
RISCVCombine.td
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVFeatures.td
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVFoldMasks.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVFrameLowering.cpp
[RISCV] Remove null terminator from CSRegs in determineCalleeSaves. NFC (#74131)
2023-12-01 14:05:55 -08:00
RISCVFrameLowering.h
…
RISCVGatherScatterLowering.cpp
…
RISCVGISel.td
[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825)
2023-12-04 13:00:34 -08:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Factor out isNonZeroLoadImmediate helper [nfc]
2023-12-15 11:20:01 -08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVInstrFormats.td
[RISCV] Move TargetOverlapConstraintType from RISCVVPseudo to TSFlags. NFC (#75877)
2023-12-18 22:25:34 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (#72000)
2023-11-22 16:43:20 -08:00
RISCVInstrInfo.cpp
[MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldClusterMemOps (#73778)
2023-12-06 15:30:48 +00:00
RISCVInstrInfo.h
[MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldClusterMemOps (#73778)
2023-12-06 15:30:48 +00:00
RISCVInstrInfo.td
[RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (#72000)
2023-11-22 16:43:20 -08:00
RISCVInstrInfoA.td
[RISCV] Add IsSignExtendingOpW to LR_W and SC_W as well. NFC
2023-11-15 09:56:36 -08:00
RISCVInstrInfoC.td
[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)
2023-10-14 08:12:46 -07:00
RISCVInstrInfoD.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoF.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoM.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Move TargetOverlapConstraintType from RISCVVPseudo to TSFlags. NFC (#75877)
2023-12-18 22:25:34 -08:00
RISCVInstrInfoVSDPatterns.td
…
RISCVInstrInfoVVLPatterns.td
[RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (#75682)
2023-12-21 14:34:49 -08:00
RISCVInstrInfoXCV.td
[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)
2023-12-17 19:29:40 +08:00
RISCVInstrInfoXSf.td
[RISCV] Fix wrong lmul for sf_vfnrclip (#76016)
2023-12-21 13:24:26 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoZb.td
[RISCV] Add more Zbs patterns for -riscv-experimental-rv64-legal-i32.
2023-11-21 23:24:00 -08:00
RISCVInstrInfoZc.td
[RISCV][NFC] Correct RISCVInstrInfoZc.td header comment - Zc* extensions no longer experimental
2023-10-10 16:41:27 +01:00
RISCVInstrInfoZfa.td
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZfh.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoZicbo.td
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Update implies for subtarget feature. (#75824)
2023-12-19 09:47:46 +08:00
RISCVISelDAGToDAG.h
[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)
2023-11-07 16:21:35 +08:00
RISCVISelLowering.cpp
[RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (#75682)
2023-12-21 14:34:49 -08:00
RISCVISelLowering.h
[RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (#75682)
2023-12-21 14:34:49 -08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
…
RISCVMacroFusion.cpp
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVMergeBaseOffset.cpp
[Target] Remove unnecessary includes (NFC)
2023-12-07 21:03:56 -08:00
RISCVMoveMerger.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVOptWInstrs.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVProcessors.td
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVPushPopOptimizer.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (#74421)
2023-12-05 07:55:01 -08:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV][NFC] Use !range bang operator (#66494)
2023-10-20 12:06:01 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVSchedRocket.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedSiFive7.td
[RISCV][MISched] Set EnableIntervals to true for SiFive7 (#75681)
2023-12-19 11:03:03 -05:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedule.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVScheduleV.td
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
RISCVScheduleZb.td
…
RISCVSubtarget.cpp
[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
2023-11-23 14:05:23 +08:00
RISCVSubtarget.h
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV][NFC] Use raw_svector_ostream to construct key of SubtargetMap (#72964)
2023-12-08 18:34:31 +08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)
2023-12-17 19:29:40 +08:00
RISCVTargetTransformInfo.h
[RISCV] Update implies for subtarget feature. (#75824)
2023-12-19 09:47:46 +08:00