0d3eee33f2
Support for below CSRs is addeed - 1. Branch Prediction Mode CSR 2. Feature Disable CSR 3. Power Dial CSR 4. RNMI CSRs spec:https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf This patch removes AltName field from SysReg class because we are now using separate class for custom vendor CSRs. Also, all use of AltName have been changed to DeprecatedName because both were interchangeably used for old names which are not in use in latest RISCV spec. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D153499
446 lines
15 KiB
TableGen
446 lines
15 KiB
TableGen
//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the symbolic operands permitted for various kinds of
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// RISC-V system instruction.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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//===----------------------------------------------------------------------===//
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// CSR (control and status register read/write) instruction options.
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//===----------------------------------------------------------------------===//
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class SysReg<string name, bits<12> op> {
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string Name = name;
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// A maximum of one deprecated name is supported right now. It generates a
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// diagnostic when the name is used to encourage software to migrate away from
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// the name.
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string DeprecatedName = "";
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bits<12> Encoding = op;
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// FIXME: add these additional fields when needed.
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// Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
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// Privilege Mode: User = 0, System = 1 or Machine = 3.
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// bits<2> ReadWrite = op{11 - 10};
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// bits<2> XMode = op{9 - 8};
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// Check Extra field name and what bits 7-6 correspond to.
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// bits<2> Extra = op{7 - 6};
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// Register number without the privilege bits.
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// bits<6> Number = op{5 - 0};
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code FeaturesRequired = [{ {} }];
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bit isRV32Only = 0;
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}
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def SysRegsList : GenericTable {
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let FilterClass = "SysReg";
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// FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
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let Fields = [
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"Name", "DeprecatedName", "Encoding", "FeaturesRequired",
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"isRV32Only",
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];
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let PrimaryKey = [ "Encoding" ];
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let PrimaryKeyName = "lookupSysRegByEncoding";
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}
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def lookupSysRegByName : SearchIndex {
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let Table = SysRegsList;
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let Key = [ "Name" ];
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}
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def lookupSysRegByDeprecatedName : SearchIndex {
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let Table = SysRegsList;
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let Key = [ "DeprecatedName" ];
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}
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class SiFiveReg<string name, bits<12> op> : SysReg<name, op>;
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def SiFiveRegsList : GenericTable {
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let FilterClass = "SiFiveReg";
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// FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
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let Fields = [
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"Name", "DeprecatedName", "Encoding", "FeaturesRequired",
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"isRV32Only",
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];
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let PrimaryKey = [ "Encoding" ];
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let PrimaryKeyName = "lookupSiFiveRegByEncoding";
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}
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def lookupSiFiveRegByName : SearchIndex {
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let Table = SiFiveRegsList;
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let Key = [ "Name" ];
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}
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def lookupSiFiveRegByDeprecatedName : SearchIndex {
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let Table = SiFiveRegsList;
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let Key = [ "DeprecatedName" ];
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}
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// The following CSR encodings match those given in Tables 2.2,
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// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
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// Volume II: Privileged Architecture.
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//===----------------------------------------------------------------------===//
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// User Floating-Point CSRs
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//===----------------------------------------------------------------------===//
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def SysRegFFLAGS : SysReg<"fflags", 0x001>;
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def SysRegFRM : SysReg<"frm", 0x002>;
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def SysRegFCSR : SysReg<"fcsr", 0x003>;
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//===----------------------------------------------------------------------===//
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// User Counter/Timers
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//===----------------------------------------------------------------------===//
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def CYCLE : SysReg<"cycle", 0xC00>;
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def TIME : SysReg<"time", 0xC01>;
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def INSTRET : SysReg<"instret", 0xC02>;
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// hpmcounter3-hpmcounter31 at 0xC03-0xC1F.
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foreach i = 3...31 in
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def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>;
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let isRV32Only = 1 in {
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def CYCLEH : SysReg<"cycleh", 0xC80>;
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def TIMEH : SysReg<"timeh", 0xC81>;
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def INSTRETH : SysReg<"instreth", 0xC82>;
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// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F.
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foreach i = 3...31 in
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def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>;
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}
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//===----------------------------------------------------------------------===//
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// Supervisor Trap Setup
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//===----------------------------------------------------------------------===//
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def : SysReg<"sstatus", 0x100>;
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def : SysReg<"sie", 0x104>;
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def : SysReg<"stvec", 0x105>;
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def : SysReg<"scounteren", 0x106>;
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def : SysReg<"stimecmp", 0x14D>;
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let isRV32Only = 1 in
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def : SysReg<"stimecmph", 0x15D>;
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//===----------------------------------------------------------------------===//
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// Supervisor Configuration
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//===----------------------------------------------------------------------===//
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def : SysReg<"senvcfg", 0x10A>;
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//===----------------------------------------------------------------------===//
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// Supervisor Trap Handling
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//===----------------------------------------------------------------------===//
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def : SysReg<"sscratch", 0x140>;
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def : SysReg<"sepc", 0x141>;
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def : SysReg<"scause", 0x142>;
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let DeprecatedName = "sbadaddr" in
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def : SysReg<"stval", 0x143>;
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def : SysReg<"sip", 0x144>;
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//===----------------------------------------------------------------------===//
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// Supervisor Protection and Translation
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//===----------------------------------------------------------------------===//
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let DeprecatedName = "sptbr" in
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def : SysReg<"satp", 0x180>;
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//===----------------------------------------------------------------------===//
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// Debug/Trace Registers
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//===----------------------------------------------------------------------===//
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def : SysReg<"scontext", 0x5A8>;
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//===----------------------------------------------------------------------===//
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// Supervisor Count Overflow (defined in Sscofpmf)
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//===----------------------------------------------------------------------===//
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def : SysReg<"scountovf", 0xDA0>;
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//===----------------------------------------------------------------------===//
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// Hypervisor Trap Setup
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//===----------------------------------------------------------------------===//
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def : SysReg<"hstatus", 0x600>;
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def : SysReg<"hedeleg", 0x602>;
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def : SysReg<"hideleg", 0x603>;
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def : SysReg<"hie", 0x604>;
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def : SysReg<"hcounteren", 0x606>;
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def : SysReg<"hgeie", 0x607>;
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//===----------------------------------------------------------------------===//
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// Hypervisor Trap Handling
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//===----------------------------------------------------------------------===//
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def : SysReg<"htval", 0x643>;
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def : SysReg<"hip", 0x644>;
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def : SysReg<"hvip", 0x645>;
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def : SysReg<"htinst", 0x64A>;
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def : SysReg<"hgeip", 0xE12>;
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//===----------------------------------------------------------------------===//
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// Hypervisor Configuration
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//===----------------------------------------------------------------------===//
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def : SysReg<"henvcfg", 0x60A>;
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let isRV32Only = 1 in
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def : SysReg<"henvcfgh", 0x61A>;
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//===----------------------------------------------------------------------===//
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// Hypervisor Protection and Translation
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//===----------------------------------------------------------------------===//
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def : SysReg<"hgatp", 0x680>;
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//===----------------------------------------------------------------------===//
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// Debug/Trace Registers
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//===----------------------------------------------------------------------===//
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def : SysReg<"hcontext", 0x6A8>;
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//===----------------------------------------------------------------------===//
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// Hypervisor Counter/Timer Virtualization Registers
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//===----------------------------------------------------------------------===//
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def : SysReg<"htimedelta", 0x605>;
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let isRV32Only = 1 in
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def : SysReg<"htimedeltah", 0x615>;
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//===----------------------------------------------------------------------===//
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// Virtual Supervisor Registers
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//===----------------------------------------------------------------------===//
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def : SysReg<"vsstatus", 0x200>;
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def : SysReg<"vsie", 0x204>;
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def : SysReg<"vstvec", 0x205>;
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def : SysReg<"vsscratch", 0x240>;
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def : SysReg<"vsepc", 0x241>;
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def : SysReg<"vscause", 0x242>;
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def : SysReg<"vstval", 0x243>;
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def : SysReg<"vsip", 0x244>;
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def : SysReg<"vstimecmp", 0x24D>;
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let isRV32Only = 1 in
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def : SysReg<"vstimecmph", 0x25D>;
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def : SysReg<"vsatp", 0x280>;
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//===----------------------------------------------------------------------===//
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// Machine Information Registers
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//===----------------------------------------------------------------------===//
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def : SysReg<"mvendorid", 0xF11>;
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def : SysReg<"marchid", 0xF12>;
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def : SysReg<"mimpid", 0xF13>;
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def : SysReg<"mhartid", 0xF14>;
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def : SysReg<"mconfigptr", 0xF15>;
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//===----------------------------------------------------------------------===//
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// Machine Trap Setup
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//===----------------------------------------------------------------------===//
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def : SysReg<"mstatus", 0x300>;
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def : SysReg<"misa", 0x301>;
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def : SysReg<"medeleg", 0x302>;
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def : SysReg<"mideleg", 0x303>;
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def : SysReg<"mie", 0x304>;
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def : SysReg<"mtvec", 0x305>;
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def : SysReg<"mcounteren", 0x306>;
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let isRV32Only = 1 in
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def : SysReg<"mstatush", 0x310>;
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//===----------------------------------------------------------------------===//
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// Machine Trap Handling
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//===----------------------------------------------------------------------===//
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def : SysReg<"mscratch", 0x340>;
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def : SysReg<"mepc", 0x341>;
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def : SysReg<"mcause", 0x342>;
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let DeprecatedName = "mbadaddr" in
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def : SysReg<"mtval", 0x343>;
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def : SysReg<"mip", 0x344>;
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def : SysReg<"mtinst", 0x34A>;
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def : SysReg<"mtval2", 0x34B>;
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//===----------------------------------------------------------------------===//
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// Machine Configuration
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//===----------------------------------------------------------------------===//
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def : SysReg<"menvcfg", 0x30A>;
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let isRV32Only = 1 in
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def : SysReg<"menvcfgh", 0x31A>;
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def : SysReg<"mseccfg", 0x747>;
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let isRV32Only = 1 in
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def : SysReg<"mseccfgh", 0x757>;
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//===----------------------------------------------------------------------===//
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// Machine Protection and Translation
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//===----------------------------------------------------------------------===//
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// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
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foreach i = 0...15 in {
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let isRV32Only = !and(i, 1) in
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def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;
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}
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// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF.
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foreach i = 0...63 in
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def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
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//===----------------------------------------------------------------------===//
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// Machine Counter and Timers
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//===----------------------------------------------------------------------===//
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def : SysReg<"mcycle", 0xB00>;
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def : SysReg<"minstret", 0xB02>;
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// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F.
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foreach i = 3...31 in
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def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>;
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let isRV32Only = 1 in {
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def: SysReg<"mcycleh", 0xB80>;
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def: SysReg<"minstreth", 0xB82>;
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// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
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foreach i = 3...31 in
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def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
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}
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//===----------------------------------------------------------------------===//
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// Machine Counter Setup
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//===----------------------------------------------------------------------===//
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let DeprecatedName = "mucounteren" in // Privileged spec v1.9.1 Name
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def : SysReg<"mcountinhibit", 0x320>;
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// mhpmevent3-mhpmevent31 at 0x323-0x33F.
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foreach i = 3...31 in
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def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
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// mhpmevent3h-mhpmevent31h at 0x723-0x73F
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foreach i = 3...31 in {
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let isRV32Only = 1 in
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def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
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}
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//===----------------------------------------------------------------------===//
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// SiFive Custom Machine Mode Registers
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//===----------------------------------------------------------------------===//
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let FeaturesRequired = [{ {RISCV::FeatureVendorXSfcie} }] in {
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def : SiFiveReg<"mnscratch", 0x350>;
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def : SiFiveReg<"mnepc", 0x351>;
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def : SiFiveReg<"mncause", 0x352>;
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def : SiFiveReg<"mnstatus", 0x353>;
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def : SiFiveReg<"mbpm", 0x7C0>;
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def : SiFiveReg<"mfd", 0x7C1>;
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def : SiFiveReg<"mpd", 0x7C8>;
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}
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//===----------------------------------------------------------------------===//
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// Debug/ Trace Registers (shared with Debug Mode)
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//===----------------------------------------------------------------------===//
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def : SysReg<"tselect", 0x7A0>;
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def : SysReg<"tdata1", 0x7A1>;
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def : SysReg<"tdata2", 0x7A2>;
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def : SysReg<"tdata3", 0x7A3>;
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def : SysReg<"mcontext", 0x7A8>;
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//===----------------------------------------------------------------------===//
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// Debug Mode Registers
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//===----------------------------------------------------------------------===//
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def : SysReg<"dcsr", 0x7B0>;
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def : SysReg<"dpc", 0x7B1>;
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// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
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// drafts of the RISC-V debug spec
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let DeprecatedName = "dscratch" in
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def : SysReg<"dscratch0", 0x7B2>;
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def : SysReg<"dscratch1", 0x7B3>;
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//===----------------------------------------------------------------------===//
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// User Vector CSRs
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//===----------------------------------------------------------------------===//
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def : SysReg<"vstart", 0x008>;
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def : SysReg<"vxsat", 0x009>;
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def SysRegVXRM : SysReg<"vxrm", 0x00A>;
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def : SysReg<"vcsr", 0x00F>;
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def SysRegVL : SysReg<"vl", 0xC20>;
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def : SysReg<"vtype", 0xC21>;
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def SysRegVLENB: SysReg<"vlenb", 0xC22>;
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//===----------------------------------------------------------------------===//
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// State Enable Extension (Smstateen)
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//===----------------------------------------------------------------------===//
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// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F,
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// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F,
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// and hstateen0h-hstateen3h at 0x61C-0x61F.
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foreach i = 0...3 in {
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def : SysReg<"sstateen"#i, !add(0x10C, i)>;
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def : SysReg<"mstateen"#i, !add(0x30C, i)>;
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let isRV32Only = 1 in
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def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>;
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def : SysReg<"hstateen"#i, !add(0x60C, i)>;
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let isRV32Only = 1 in
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def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
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}
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//===-----------------------------------------------
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// Entropy Source CSR
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//===-----------------------------------------------
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def SEED : SysReg<"seed", 0x015>;
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//===-----------------------------------------------
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// Advanced Interrupt Architecture
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//===-----------------------------------------------
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// Machine-level CSRs
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def : SysReg<"miselect", 0x350>;
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def : SysReg<"mireg", 0x351>;
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def : SysReg<"mtopei", 0x35C>;
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def : SysReg<"mtopi", 0xFB0>;
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def : SysReg<"mvien", 0x308>;
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def : SysReg<"mvip", 0x309>;
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let isRV32Only = 1 in {
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def : SysReg<"midelegh", 0x313>;
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def : SysReg<"mieh", 0x314>;
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def : SysReg<"mvienh", 0x318>;
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def : SysReg<"mviph", 0x319>;
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def : SysReg<"miph", 0x354>;
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} // isRV32Only
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// Supervisor-level CSRs
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def : SysReg<"siselect", 0x150>;
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def : SysReg<"sireg", 0x151>;
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def : SysReg<"stopei", 0x15C>;
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def : SysReg<"stopi", 0xDB0>;
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let isRV32Only = 1 in {
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def : SysReg<"sieh", 0x114>;
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def : SysReg<"siph", 0x154>;
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} // isRV32Only
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// Hypervisor and VS CSRs
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def : SysReg<"hvien", 0x608>;
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def : SysReg<"hvictl", 0x609>;
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def : SysReg<"hviprio1", 0x646>;
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def : SysReg<"hviprio2", 0x647>;
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def : SysReg<"vsiselect", 0x250>;
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def : SysReg<"vsireg", 0x251>;
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def : SysReg<"vstopei", 0x25C>;
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def : SysReg<"vstopi", 0xEB0>;
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let isRV32Only = 1 in {
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def : SysReg<"hidelegh", 0x613>;
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def : SysReg<"hvienh", 0x618>;
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def : SysReg<"hviph", 0x655>;
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def : SysReg<"hviprio1h", 0x656>;
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def : SysReg<"hviprio2h", 0x657>;
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def : SysReg<"vsieh", 0x214>;
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def : SysReg<"vsiph", 0x254>;
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} // isRV32Only
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// Jump Vector Table CSR
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//===-----------------------------------------------
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def : SysReg<"jvt", 0x017>;
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