99809f4377
For `CSR_Interrupt`, we can generate the register list via a single `sequence`. For `CSR_XLEN_F32_Interrupt` and `CSR_XLEN_F64_Interrupt`, I don't see the reason why we need to keep the order the same as how we used to allocate registers (and we have changed the order in D146488), so I fold them into one `sequence`. There are some *.ll changes because of the order change. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D154837
41 lines
1.7 KiB
TableGen
41 lines
1.7 KiB
TableGen
//===-- RISCVCallingConv.td - Calling Conventions RISC-V ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the RISC-V architecture.
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//
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//===----------------------------------------------------------------------===//
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// The RISC-V calling convention is handled with custom code in
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// RISCVISelLowering.cpp (CC_RISCV).
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def CSR_ILP32_LP64
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: CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
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def CSR_ILP32F_LP64F
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
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def CSR_ILP32D_LP64D
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: CalleeSavedRegs<(add CSR_ILP32_LP64,
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F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
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// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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// Interrupt handler needs to save/restore all registers that are used,
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// both Caller and Callee saved registers.
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def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 3, 31))>;
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// Same as CSR_Interrupt, but including all 32-bit FP registers.
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def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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(sequence "F%u_F", 0, 31))>;
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// Same as CSR_Interrupt, but including all 64-bit FP registers.
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def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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(sequence "F%u_D", 0, 31))>;
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