d64d5ea102
After #71534 and #72052, the transform `zext -> zext nneg` in `RISCVCodeGenPrepare` is redundant.
133 lines
3.8 KiB
C++
133 lines
3.8 KiB
C++
//===----- RISCVCodeGenPrepare.cpp ----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a RISC-V specific version of CodeGenPrepare.
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// It munges the code in the input function to better prepare it for
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// SelectionDAG-based code generation. This works around limitations in it's
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// basic-block-at-a-time approach.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/InstVisitor.h"
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#include "llvm/IR/PatternMatch.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-codegenprepare"
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#define PASS_NAME "RISC-V CodeGenPrepare"
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namespace {
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class RISCVCodeGenPrepare : public FunctionPass,
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public InstVisitor<RISCVCodeGenPrepare, bool> {
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const DataLayout *DL;
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const RISCVSubtarget *ST;
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public:
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static char ID;
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RISCVCodeGenPrepare() : FunctionPass(ID) {}
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bool runOnFunction(Function &F) override;
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StringRef getPassName() const override { return PASS_NAME; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<TargetPassConfig>();
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}
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bool visitInstruction(Instruction &I) { return false; }
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bool visitAnd(BinaryOperator &BO);
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};
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} // end anonymous namespace
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// Try to optimize (i64 (and (zext/sext (i32 X), C1))) if C1 has bit 31 set,
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// but bits 63:32 are zero. If we know that bit 31 of X is 0, we can fill
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// the upper 32 bits with ones.
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bool RISCVCodeGenPrepare::visitAnd(BinaryOperator &BO) {
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if (!ST->is64Bit())
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return false;
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if (!BO.getType()->isIntegerTy(64))
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return false;
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auto canBeSignExtend = [](Instruction *I) {
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if (isa<SExtInst>(I))
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return true;
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if (isa<ZExtInst>(I))
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return I->hasNonNeg();
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return false;
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};
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// Left hand side should be a sext or zext nneg.
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Instruction *LHS = dyn_cast<Instruction>(BO.getOperand(0));
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if (!LHS || !canBeSignExtend(LHS))
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return false;
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Value *LHSSrc = LHS->getOperand(0);
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if (!LHSSrc->getType()->isIntegerTy(32))
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return false;
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// Right hand side should be a constant.
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Value *RHS = BO.getOperand(1);
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auto *CI = dyn_cast<ConstantInt>(RHS);
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if (!CI)
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return false;
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uint64_t C = CI->getZExtValue();
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// Look for constants that fit in 32 bits but not simm12, and can be made
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// into simm12 by sign extending bit 31. This will allow use of ANDI.
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// TODO: Is worth making simm32?
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if (!isUInt<32>(C) || isInt<12>(C) || !isInt<12>(SignExtend64<32>(C)))
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return false;
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// Sign extend the constant and replace the And operand.
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C = SignExtend64<32>(C);
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BO.setOperand(1, ConstantInt::get(LHS->getType(), C));
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return true;
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}
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bool RISCVCodeGenPrepare::runOnFunction(Function &F) {
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if (skipFunction(F))
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return false;
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auto &TPC = getAnalysis<TargetPassConfig>();
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auto &TM = TPC.getTM<RISCVTargetMachine>();
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ST = &TM.getSubtarget<RISCVSubtarget>(F);
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DL = &F.getParent()->getDataLayout();
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bool MadeChange = false;
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for (auto &BB : F)
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for (Instruction &I : llvm::make_early_inc_range(BB))
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MadeChange |= visit(I);
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return MadeChange;
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}
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INITIALIZE_PASS_BEGIN(RISCVCodeGenPrepare, DEBUG_TYPE, PASS_NAME, false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_END(RISCVCodeGenPrepare, DEBUG_TYPE, PASS_NAME, false, false)
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char RISCVCodeGenPrepare::ID = 0;
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FunctionPass *llvm::createRISCVCodeGenPreparePass() {
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return new RISCVCodeGenPrepare();
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}
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