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clang-p2996/llvm/test/CodeGen
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Momchil Velikov 4b6968952e [AArch64] Implement spill/fill of predicate pair register classes (#76068) 
We are getting ICE with, e.g.
```
#include <arm_sve.h>

 void g();
 svboolx2_t f0(int64_t i, int64_t n) {
     svboolx2_t r = svwhilelt_b16_x2(i, n);
     g();
     return r;
 }
```
2023-12-22 15:54:12 +00:00
..
AArch64
[AArch64] Implement spill/fill of predicate pair register classes (#76068)
2023-12-22 15:54:12 +00:00
AMDGPU
DAG: Implement promotion for strict_fpextend (#74310)
2023-12-22 17:15:52 +07:00
ARC
…
ARM
[ARM][FPEnv] Lowering of fpmode intrinsics (#74054)
2023-12-18 18:57:36 +07:00
AVR
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
BPF
[BPF] improve error handling by custom lowering & fail() (#75088)
2023-12-13 13:41:52 +08:00
CSKY
[CSKY,test] Update switch.ll
2023-10-31 15:47:05 -07:00
DirectX
[HLSL][DirectX] Move handling of resource element types into the frontend
2023-12-18 11:43:52 -07:00
Generic
[CodeGen] Update DwarfEHPreparePass references in CodeGenPassBuilder.h (#74068)
2023-12-11 09:26:01 +08:00
Hexagon
[Tests] Add disjoint flag to some tests (NFC)
2023-12-05 14:09:36 +01:00
Inputs
…
Lanai
[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=
2023-09-11 15:11:01 -07:00
LoongArch
[LoongArch] Add codegen support for [X]VF{MSUB/NMADD/NMSUB}.{S/D} instructions (#74819)
2023-12-11 10:37:22 +08:00
M68k
[M68k] Emit RTE for interrupt handler. (#72787)
2023-12-04 15:11:00 +08:00
Mips
[SelectionDAG] Use getVectorElementPointer in DAGCombiner::replaceStoreOfInsertLoad. (#74249)
2023-12-14 20:25:16 -08:00
MIR
MachineVerifier: Reject extra non-register operands on instructions (#73758)
2023-11-30 22:33:42 +09:00
MLRegAlloc
[mlgo] Fix test post PR #73899
2023-12-01 09:05:22 -08:00
MSP430
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
NVPTX
[llvm][NVPTX] Inform that 'DYNAMIC_STACKALLOC' is unsupported (#74684)
2023-12-14 22:06:22 -05:00
PowerPC
[XCOFF] Use RLDs to print branches even without -r (#74342)
2023-12-21 08:17:32 -06:00
RISCV
[RISCV] Fix macro-fusions.mir
2023-12-22 14:49:59 +08:00
SPARC
[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)
2023-10-10 20:34:20 +03:00
SPIRV
[SPIR-V][NFC] Require asserts on 2 tests (#75087)
2023-12-14 15:17:11 -05:00
SystemZ
[SystemZ] Test improvements for atomic load/store instructions (NFC). (#75630)
2023-12-21 20:48:00 +01:00
Thumb
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
Thumb2
[ARM] Check all terms in emitPopInst when clearing Restored for LR. (#75527)
2023-12-20 16:56:15 +01:00
VE
BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreads
2023-10-24 20:27:39 -07:00
WebAssembly
[CodeGen] Rename winehprepare -> win-eh-prepare (#75024)
2023-12-11 13:55:27 +08:00
WinCFGuard
…
WinEH
[CodeGen] Rename winehprepare -> win-eh-prepare (#75024)
2023-12-11 13:55:27 +08:00
X86
Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"
2023-12-22 16:46:22 +07:00
XCore
[XCore] Set MaxAtomicSizeInBitsSupported to 0 (#74389)
2023-12-05 12:51:01 -05:00