e4a4122eb6
Remove support for zext and sext constant expressions. All places creating them have been removed beforehand, so this just removes the APIs and uses of these constant expressions in tests. There is some additional cleanup that can be done on top of this, e.g. we can remove the ZExtInst vs ZExtOperator footgun. This is part of https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179.
660 lines
25 KiB
LLVM
660 lines
25 KiB
LLVM
; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
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; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS
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; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck -enable-var-scope %s --check-prefix=OPTALL --check-prefix=DISABLE
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; CodeGenPrepare should move the zext into the block with the load
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; so that SelectionDAG can select it with the load.
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;
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; OPTALL-LABEL: @foo
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; OPTALL: store i32 [[ZEXT]], ptr %q
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; OPTALL: ret
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define void @foo(ptr %p, ptr %q) {
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entry:
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%t = load i8, ptr %p
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %t to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload is an operation with only one
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; argument to explicitly extend is in the way.
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; OPTALL-LABEL: @promoteOneArg
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
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; Make sure the operation is not promoted when the promotion pass is disabled.
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteOneArg(ptr %p, ptr %q) {
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entry:
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%t = load i8, ptr %p
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%add = add nuw i8 %t, 2
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload is an operation with only one
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; argument to explicitly extend is in the way.
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; Version with sext.
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; OPTALL-LABEL: @promoteOneArgSExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteOneArgSExt(ptr %p, ptr %q) {
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entry:
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%t = load i8, ptr %p
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%add = add nsw i8 %t, 2
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload is an operation with two
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; arguments to explicitly extend is in the way.
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; Extending %add will create two extensions:
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; 1. One for %b.
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; 2. One for %t.
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; #1 will not be removed as we do not know anything about %b.
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; #2 may not be merged with the load because %t is used in a comparison.
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; Since two extensions may be emitted in the end instead of one before the
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; transformation, the regular heuristic does not apply the optimization.
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;
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; OPTALL-LABEL: @promoteTwoArgZext
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
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;
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteTwoArgZext(ptr %p, ptr %q, i8 %b) {
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entry:
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%t = load i8, ptr %p
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%add = add nuw i8 %t, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload is an operation with two
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; arguments to explicitly extend is in the way.
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; Version with sext.
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; OPTALL-LABEL: @promoteTwoArgSExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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;
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; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
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; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXTLD]], [[SEXTB]]
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;
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
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;
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteTwoArgSExt(ptr %p, ptr %q, i8 %b) {
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entry:
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%t = load i8, ptr %p
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%add = add nsw i8 %t, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we do not a zextload if we need to introduce more than
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; one additional extension.
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; OPTALL-LABEL: @promoteThreeArgZext
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
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; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
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; STRESS-NEXT: [[ZEXTC:%[a-zA-Z_0-9-]+]] = zext i8 %c to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]]
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;
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; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
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; NONSTRESS-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[TMP]], %c
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; DISABLE: add nuw i8
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
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;
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteThreeArgZext(ptr %p, ptr %q, i8 %b, i8 %c) {
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entry:
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%t = load i8, ptr %p
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%tmp = add nuw i8 %t, %b
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%add = add nuw i8 %tmp, %c
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i8 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a zextload after promoting and merging
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; two extensions.
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; OPTALL-LABEL: @promoteMergeExtArgZExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
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;
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; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
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;
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; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
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;
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteMergeExtArgZExt(ptr %p, ptr %q, i16 %b) {
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entry:
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%t = load i8, ptr %p
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%ext = zext i8 %t to i16
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%add = add nuw i16 %ext, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = zext i16 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to form a sextload after promoting and merging
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; two extensions.
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; Version with sext.
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; OPTALL-LABEL: @promoteMergeExtArgSExt
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
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;
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; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
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; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32
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; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXTLD]], [[ZEXTB]]
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;
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; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
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; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
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;
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; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
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; OPTALL: store i32 [[RES]], ptr %q
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; OPTALL: ret
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define void @promoteMergeExtArgSExt(ptr %p, ptr %q, i16 %b) {
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entry:
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%t = load i8, ptr %p
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%ext = zext i8 %t to i16
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%add = add nsw i16 %ext, %b
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%a = icmp slt i8 %t, 20
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br i1 %a, label %true, label %false
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true:
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%s = sext i16 %add to i32
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store i32 %s, ptr %q
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ret void
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false:
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ret void
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}
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; Check that we manage to catch all the extload opportunities that are exposed
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; by the different iterations of codegen prepare.
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; Moreover, check that we do not promote more than we need to.
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; Here is what is happening in this test (not necessarly in this order):
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; 1. We try to promote the operand of %sextadd.
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; a. This creates one sext of %ld2 and one of %zextld
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; b. The sext of %ld2 can be combine with %ld2, so we remove one sext but
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; introduced one. This is fine with the current heuristic: neutral.
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; => We have one zext of %zextld left and we created one sext of %ld2.
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; 2. We try to promote the operand of %sextaddza.
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; a. This creates one sext of %zexta and one of %zextld
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; b. The sext of %zexta can be combined with the zext of %a.
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; c. The sext of %zextld leads to %ld and can be combined with it. This is
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; done by promoting %zextld. This is fine with the current heuristic:
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; neutral.
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; => We have created a new zext of %ld and we created one sext of %zexta.
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; 3. We try to promote the operand of %sextaddb.
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; a. This creates one sext of %b and one of %zextld
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; b. The sext of %b is a dead-end, nothing to be done.
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; c. Same thing as 2.c. happens.
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; => We have created a new zext of %ld and we created one sext of %b.
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; 4. We try to promote the operand of the zext of %zextld introduced in #1.
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; a. Same thing as 2.c. happens.
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; b. %zextld does not have any other uses. It is dead coded.
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; => We have created a new zext of %ld and we removed a zext of %zextld and
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; a zext of %ld.
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; Currently we do not try to reuse existing extensions, so in the end we have
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; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
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;
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; OPTALL-LABEL: @severalPromotions
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %addr1
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; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
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; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
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; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, ptr %addr2
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; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64
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; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_3]]
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; OPT-NEXT: [[ZEXTLD1_4:%[a-zA-Z_0-9-]+]] = zext i8 %a to i64
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; OPT-NEXT: [[RESZA:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXTLD1_4]], [[ZEXTLD1_2]]
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; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
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; OPT-NEXT: [[RESB:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTB]], [[ZEXTLD1_1]]
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;
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; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32
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; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
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; DISABLE: [[ADDZA:%[a-zA-Z_0-9-]+]] = add nsw i32
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; DISABLE: [[RESZA:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDZA]] to i64
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; DISABLE: [[ADDB:%[a-zA-Z_0-9-]+]] = add nsw i32
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; DISABLE: [[RESB:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDB]] to i64
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;
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; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]])
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; OPTALL: ret
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define void @severalPromotions(ptr %addr1, ptr %addr2, i8 %a, i32 %b) {
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%ld = load i8, ptr %addr1
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%zextld = zext i8 %ld to i32
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%ld2 = load i32, ptr %addr2
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%add = add nsw i32 %ld2, %zextld
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%sextadd = sext i32 %add to i64
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%zexta = zext i8 %a to i32
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%addza = add nsw i32 %zexta, %zextld
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%sextaddza = sext i32 %addza to i64
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%addb = add nsw i32 %b, %zextld
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%sextaddb = sext i32 %addb to i64
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call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
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ret void
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}
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declare void @dummy(i64, i64, i64)
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; Make sure we do not try to promote vector types since the type promotion
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; helper does not support them for now.
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; OPTALL-LABEL: @vectorPromotion
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; OPTALL: [[SHL:%[a-zA-Z_0-9-]+]] = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
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; OPTALL: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext <2 x i32> [[SHL]] to <2 x i64>
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; OPTALL: ret
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define void @vectorPromotion() {
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entry:
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%a = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
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%b = zext <2 x i32> %a to <2 x i64>
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ret void
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}
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@a = common global i32 0, align 4
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@c = common global [2 x i32] zeroinitializer, align 4
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; Make sure we support promotion of operands that produces a Value as opposed
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; to an instruction.
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; This used to cause a crash.
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; OPTALL-LABEL: @promotionOfArgEndsUpInValue
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; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, ptr %addr
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;
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; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
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; OPT-NEXT: [[SEXT2:%[a-zA-Z_0-9-]+]] = zext i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i32
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; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], [[SEXT2]]
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;
|
|
; DISABLE-NEXT: [[EXT:%[a-zA-Z_0-9-]+]] = zext i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16
|
|
; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], [[EXT]]
|
|
; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
|
|
;
|
|
; OPTALL-NEXT: ret i32 [[RES]]
|
|
define i32 @promotionOfArgEndsUpInValue(ptr %addr) {
|
|
entry:
|
|
%val = load i16, ptr %addr
|
|
%ext = zext i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16
|
|
%add = add nuw nsw i16 %val, %ext
|
|
%conv3 = sext i16 %add to i32
|
|
ret i32 %conv3
|
|
}
|
|
|
|
; Check that we see that one zext can be derived from the other for free.
|
|
; OPTALL-LABEL: @promoteTwoArgZextWithSourceExtendedTwice
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
|
|
; OPT-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], 12
|
|
; OPT-NEXT: store i32 [[RES32]], ptr %addr
|
|
; OPT-NEXT: store i64 [[RES64]], ptr %q
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[RES2_32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], 12
|
|
; DISABLE-NEXT: store i32 [[RES32]], ptr %addr
|
|
; DISABLE-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES2_32]] to i64
|
|
; DISABLE-NEXT: store i64 [[ZEXT64]], ptr %q
|
|
;
|
|
; OPTALL-NEXT: ret void
|
|
define void @promoteTwoArgZextWithSourceExtendedTwice(ptr %p, ptr %q, i32 %b, ptr %addr) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nuw i32 %zextt, %b
|
|
%add2 = add nuw i32 %zextt, 12
|
|
store i32 %add, ptr %addr
|
|
%s = zext i32 %add2 to i64
|
|
store i64 %s, ptr %q
|
|
ret void
|
|
}
|
|
|
|
; Check that we do not increase the cost of the code.
|
|
; The input has one free zext and one free sext. If we would have promoted
|
|
; all the way through the load we would end up with a free zext and a
|
|
; non-free sext (of %b).
|
|
; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
|
|
; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
|
|
; STRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32
|
|
;
|
|
; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, ptr %addr, i64 [[IDX64]]
|
|
; OPTALL-NEXT: store i32 [[RES32]], ptr [[GEP]]
|
|
; OPTALL-NEXT: ret void
|
|
define void @doNotPromoteFreeSExtFromAddrMode(ptr %p, i32 %b, ptr %addr) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nsw i32 %zextt, %b
|
|
%idx64 = sext i32 %add to i64
|
|
%staddr = getelementptr inbounds i32, ptr %addr, i64 %idx64
|
|
store i32 %add, ptr %staddr
|
|
ret void
|
|
}
|
|
|
|
; Check that we do not increase the cost of the code.
|
|
; The input has one free zext and one free sext. If we would have promoted
|
|
; all the way through the load we would end up with a free zext and a
|
|
; non-free sext (of %b).
|
|
; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode64
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
|
|
; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
|
|
;
|
|
; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i64, ptr %addr, i64 [[IDX64]]
|
|
; OPTALL-NEXT: store i64 %stuff, ptr [[GEP]]
|
|
; OPTALL-NEXT: ret void
|
|
define void @doNotPromoteFreeSExtFromAddrMode64(ptr %p, i32 %b, ptr %addr, i64 %stuff) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nsw i32 %zextt, %b
|
|
%idx64 = sext i32 %add to i64
|
|
%staddr = getelementptr inbounds i64, ptr %addr, i64 %idx64
|
|
store i64 %stuff, ptr %staddr
|
|
ret void
|
|
}
|
|
|
|
; Check that we do not increase the cost of the code.
|
|
; The input has one free zext and one free sext. If we would have promoted
|
|
; all the way through the load we would end up with a free zext and a
|
|
; non-free sext (of %b).
|
|
; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode128
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
|
|
; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
|
|
;
|
|
; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i128, ptr %addr, i64 [[IDX64]]
|
|
; OPTALL-NEXT: store i128 %stuff, ptr [[GEP]]
|
|
; OPTALL-NEXT: ret void
|
|
define void @doNotPromoteFreeSExtFromAddrMode128(ptr %p, i32 %b, ptr %addr, i128 %stuff) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nsw i32 %zextt, %b
|
|
%idx64 = sext i32 %add to i64
|
|
%staddr = getelementptr inbounds i128, ptr %addr, i64 %idx64
|
|
store i128 %stuff, ptr %staddr
|
|
ret void
|
|
}
|
|
|
|
|
|
; Check that we do not increase the cost of the code.
|
|
; The input has one free zext and one free sext. If we would have promoted
|
|
; all the way through the load we would end up with a free zext and a
|
|
; non-free sext (of %b).
|
|
; OPTALL-LABEL: @promoteSExtFromAddrMode256
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
|
|
; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i256, ptr %addr, i64 [[IDX64]]
|
|
; OPTALL-NEXT: store i256 %stuff, ptr [[GEP]]
|
|
; OPTALL-NEXT: ret void
|
|
define void @promoteSExtFromAddrMode256(ptr %p, i32 %b, ptr %addr, i256 %stuff) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nsw i32 %zextt, %b
|
|
%idx64 = sext i32 %add to i64
|
|
%staddr = getelementptr inbounds i256, ptr %addr, i64 %idx64
|
|
store i256 %stuff, ptr %staddr
|
|
ret void
|
|
}
|
|
|
|
; Check that we do not increase the cost of the code.
|
|
; The input has one free zext and one free zext.
|
|
; When we promote all the way through the load, we end up with
|
|
; a free zext and a non-free zext (of %b).
|
|
; However, the current target lowering says zext i32 to i64 is free
|
|
; so the promotion happens because the cost did not change and may
|
|
; expose more opportunities.
|
|
; This would need to be fixed at some point.
|
|
; OPTALL-LABEL: @doNotPromoteFreeZExtFromAddrMode
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; This transformation should really happen only for stress mode.
|
|
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
|
|
; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
|
|
; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, ptr %addr, i64 [[IDX64]]
|
|
; OPTALL-NEXT: store i32 [[RES32]], ptr [[GEP]]
|
|
; OPTALL-NEXT: ret void
|
|
define void @doNotPromoteFreeZExtFromAddrMode(ptr %p, i32 %b, ptr %addr) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nuw i32 %zextt, %b
|
|
%idx64 = zext i32 %add to i64
|
|
%staddr = getelementptr inbounds i32, ptr %addr, i64 %idx64
|
|
store i32 %add, ptr %staddr
|
|
ret void
|
|
}
|
|
|
|
; OPTALL-LABEL: @doNotPromoteFreeSExtFromShift
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
|
|
; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]]
|
|
;
|
|
; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = shl i64 [[IDX64]], 12
|
|
; OPTALL-NEXT: ret i64 %staddr
|
|
define i64 @doNotPromoteFreeSExtFromShift(ptr %p, i32 %b) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nsw i32 %zextt, %b
|
|
%idx64 = sext i32 %add to i64
|
|
%staddr = shl i64 %idx64, 12
|
|
ret i64 %staddr
|
|
}
|
|
|
|
; Same comment as doNotPromoteFreeZExtFromAddrMode.
|
|
; OPTALL-LABEL: @doNotPromoteFreeZExtFromShift
|
|
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
|
|
;
|
|
; This transformation should really happen only for stress mode.
|
|
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
|
|
; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
|
|
; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
|
|
;
|
|
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
|
|
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
|
|
; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = shl i64 [[IDX64]], 12
|
|
; OPTALL-NEXT: ret i64 %staddr
|
|
define i64 @doNotPromoteFreeZExtFromShift(ptr %p, i32 %b) {
|
|
entry:
|
|
%t = load i8, ptr %p
|
|
%zextt = zext i8 %t to i32
|
|
%add = add nuw i32 %zextt, %b
|
|
%idx64 = zext i32 %add to i64
|
|
%staddr = shl i64 %idx64, 12
|
|
ret i64 %staddr
|
|
}
|
|
|
|
; The input has one free zext and one non-free sext.
|
|
; When we promote all the way through to the load, we end up with
|
|
; a free zext, a free sext (%ld1), and a non-free sext (of %cst).
|
|
; However, we when generate load pair and the free sext(%ld1) becomes
|
|
; non-free. So technically, we trade a non-free sext to two non-free
|
|
; sext.
|
|
; This would need to be fixed at some point.
|
|
; OPTALL-LABEL: @doNotPromoteBecauseOfPairedLoad
|
|
; OPTALL: [[LD0:%[a-zA-Z_0-9-]+]] = load i32, ptr %p
|
|
; OPTALL: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, ptr %p, i64 1
|
|
; OPTALL: [[LD1:%[a-zA-Z_0-9-]+]] = load i32, ptr [[GEP]]
|
|
;
|
|
; This transformation should really happen only for stress mode.
|
|
; OPT-NEXT: [[SEXTLD1:%[a-zA-Z_0-9-]+]] = sext i32 [[LD1]] to i64
|
|
; OPT-NEXT: [[SEXTCST:%[a-zA-Z_0-9-]+]] = sext i32 %cst to i64
|
|
; OPT-NEXT: [[SEXTRES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD1]], [[SEXTCST]]
|
|
;
|
|
; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[LD1]], %cst
|
|
; DISABLE-NEXT: [[SEXTRES:%[a-zA-Z_0-9-]+]] = sext i32 [[RES]] to i64
|
|
;
|
|
; OPTALL-NEXT: [[ZEXTLD0:%[a-zA-Z_0-9-]+]] = zext i32 [[LD0]] to i64
|
|
; OPTALL-NEXT: [[FINAL:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTRES]], [[ZEXTLD0]]
|
|
; OPTALL-NEXT: ret i64 [[FINAL]]
|
|
define i64 @doNotPromoteBecauseOfPairedLoad(ptr %p, i32 %cst) {
|
|
%ld0 = load i32, ptr %p
|
|
%idxLd1 = getelementptr inbounds i32, ptr %p, i64 1
|
|
%ld1 = load i32, ptr %idxLd1
|
|
%res = add nsw i32 %ld1, %cst
|
|
%sextres = sext i32 %res to i64
|
|
%zextLd0 = zext i32 %ld0 to i64
|
|
%final = add i64 %sextres, %zextLd0
|
|
ret i64 %final
|
|
}
|
|
|
|
define i64 @promoteZextShl(i1 %c, ptr %P) {
|
|
entry:
|
|
; OPTALL-LABEL: promoteZextShl
|
|
; OPTALL: entry:
|
|
; OPT: %[[LD:.*]] = load i16, ptr %P
|
|
; OPT: %[[EXT:.*]] = zext i16 %[[LD]] to i64
|
|
; OPT: if.then:
|
|
; OPT: shl nsw i64 %[[EXT]], 1
|
|
; DISABLE: if.then:
|
|
; DISABLE: %r = sext i32 %shl2 to i64
|
|
%ld = load i16, ptr %P
|
|
br i1 %c, label %end, label %if.then
|
|
if.then:
|
|
%z = zext i16 %ld to i32
|
|
%shl2 = shl nsw i32 %z, 1
|
|
%r = sext i32 %shl2 to i64
|
|
ret i64 %r
|
|
end:
|
|
ret i64 0
|
|
}
|