db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
242 lines
6.6 KiB
LLVM
242 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,SDISEL
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; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,GISEL
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; Ensure chains of comparisons produce chains of `ccmp`
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; (x0 < x1) && (x2 > x3)
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define i32 @cmp_and2(i32 %0, i32 %1, i32 %2, i32 %3) {
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; SDISEL-LABEL: cmp_and2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #0, lo
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; SDISEL-NEXT: cset w0, hi
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_and2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: and w0, w8, w9
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; GISEL-NEXT: ret
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%5 = icmp ult i32 %0, %1
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%6 = icmp ugt i32 %2, %3
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%7 = select i1 %5, i1 %6, i1 false
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%8 = zext i1 %7 to i32
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ret i32 %8
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}
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; (x0 < x1) && (x2 > x3) && (x4 != x5)
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define i32 @cmp_and3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {
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; SDISEL-LABEL: cmp_and3:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #0, lo
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; SDISEL-NEXT: ccmp w4, w5, #4, hi
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_and3:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: and w8, w8, w9
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: and w0, w8, w9
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; GISEL-NEXT: ret
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%7 = icmp ult i32 %0, %1
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%8 = icmp ugt i32 %2, %3
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%9 = select i1 %7, i1 %8, i1 false
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%10 = icmp ne i32 %4, %5
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%11 = select i1 %9, i1 %10, i1 false
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%12 = zext i1 %11 to i32
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ret i32 %12
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}
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; (x0 < x1) && (x2 > x3) && (x4 != x5) && (x6 == x7)
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define i32 @cmp_and4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) {
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; SDISEL-LABEL: cmp_and4:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w2, w3
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; SDISEL-NEXT: ccmp w0, w1, #2, hi
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; SDISEL-NEXT: ccmp w4, w5, #4, lo
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; SDISEL-NEXT: ccmp w6, w7, #0, ne
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; SDISEL-NEXT: cset w0, eq
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_and4:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w8, hi
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w9, lo
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: cset w10, ne
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; GISEL-NEXT: cmp w6, w7
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; GISEL-NEXT: and w8, w8, w9
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; GISEL-NEXT: cset w11, eq
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; GISEL-NEXT: and w9, w10, w11
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; GISEL-NEXT: and w0, w8, w9
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; GISEL-NEXT: ret
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%9 = icmp ugt i32 %2, %3
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%10 = icmp ult i32 %0, %1
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%11 = select i1 %9, i1 %10, i1 false
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%12 = icmp ne i32 %4, %5
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%13 = select i1 %11, i1 %12, i1 false
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%14 = icmp eq i32 %6, %7
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%15 = select i1 %13, i1 %14, i1 false
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%16 = zext i1 %15 to i32
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ret i32 %16
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}
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; (x0 < x1) || (x2 > x3)
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define i32 @cmp_or2(i32 %0, i32 %1, i32 %2, i32 %3) {
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; SDISEL-LABEL: cmp_or2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #0, hs
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_or2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w0, w8, w9
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; GISEL-NEXT: ret
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%5 = icmp ult i32 %0, %1
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%6 = icmp ne i32 %2, %3
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%7 = select i1 %5, i1 true, i1 %6
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%8 = zext i1 %7 to i32
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ret i32 %8
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}
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; (x0 < x1) || (x2 > x3) || (x4 != x5)
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define i32 @cmp_or3(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5) {
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; SDISEL-LABEL: cmp_or3:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #2, hs
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; SDISEL-NEXT: ccmp w4, w5, #0, ls
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_or3:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w0, w8, w9
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; GISEL-NEXT: ret
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%7 = icmp ult i32 %0, %1
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%8 = icmp ugt i32 %2, %3
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%9 = select i1 %7, i1 true, i1 %8
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%10 = icmp ne i32 %4, %5
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%11 = select i1 %9, i1 true, i1 %10
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%12 = zext i1 %11 to i32
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ret i32 %12
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}
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; (x0 < x1) || (x2 > x3) || (x4 != x5) || (x6 == x7)
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define i32 @cmp_or4(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) {
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; SDISEL-LABEL: cmp_or4:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: cmp w0, w1
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; SDISEL-NEXT: ccmp w2, w3, #2, hs
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; SDISEL-NEXT: ccmp w4, w5, #0, ls
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; SDISEL-NEXT: ccmp w6, w7, #4, eq
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; SDISEL-NEXT: cset w0, eq
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: cmp_or4:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, w1
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; GISEL-NEXT: cset w8, lo
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; GISEL-NEXT: cmp w2, w3
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; GISEL-NEXT: cset w9, hi
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; GISEL-NEXT: cmp w4, w5
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; GISEL-NEXT: cset w10, ne
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; GISEL-NEXT: cmp w6, w7
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: cset w11, eq
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; GISEL-NEXT: orr w9, w10, w11
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; GISEL-NEXT: orr w0, w8, w9
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; GISEL-NEXT: ret
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%9 = icmp ult i32 %0, %1
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%10 = icmp ugt i32 %2, %3
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%11 = select i1 %9, i1 true, i1 %10
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%12 = icmp ne i32 %4, %5
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%13 = select i1 %11, i1 true, i1 %12
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%14 = icmp eq i32 %6, %7
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%15 = select i1 %13, i1 true, i1 %14
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%16 = zext i1 %15 to i32
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ret i32 %16
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}
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; (x0 != 0) || (x1 != 0)
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define i32 @true_or2(i32 %0, i32 %1) {
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; SDISEL-LABEL: true_or2:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w0, w1
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; SDISEL-NEXT: cmp w8, #0
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: true_or2:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, #0
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; GISEL-NEXT: cset w8, ne
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; GISEL-NEXT: cmp w1, #0
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w0, w8, w9
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; GISEL-NEXT: ret
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%3 = icmp ne i32 %0, 0
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%4 = icmp ne i32 %1, 0
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%5 = select i1 %3, i1 true, i1 %4
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%6 = zext i1 %5 to i32
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ret i32 %6
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}
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; (x0 != 0) || (x1 != 0) || (x2 != 0)
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define i32 @true_or3(i32 %0, i32 %1, i32 %2) {
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; SDISEL-LABEL: true_or3:
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; SDISEL: // %bb.0:
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; SDISEL-NEXT: orr w8, w0, w1
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; SDISEL-NEXT: orr w8, w8, w2
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; SDISEL-NEXT: cmp w8, #0
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; SDISEL-NEXT: cset w0, ne
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; SDISEL-NEXT: ret
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;
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; GISEL-LABEL: true_or3:
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; GISEL: // %bb.0:
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; GISEL-NEXT: cmp w0, #0
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; GISEL-NEXT: cset w8, ne
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; GISEL-NEXT: cmp w1, #0
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: cmp w2, #0
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; GISEL-NEXT: orr w8, w8, w9
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; GISEL-NEXT: cset w9, ne
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; GISEL-NEXT: orr w0, w8, w9
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; GISEL-NEXT: ret
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%4 = icmp ne i32 %0, 0
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%5 = icmp ne i32 %1, 0
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%6 = select i1 %4, i1 true, i1 %5
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%7 = icmp ne i32 %2, 0
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%8 = select i1 %6, i1 true, i1 %7
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%9 = zext i1 %8 to i32
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ret i32 %9
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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