db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
137 lines
5.7 KiB
LLVM
137 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: dup v2.2s, v0.s[1]
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; CHECK-NEXT: mov v1.16b, v2.16b
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; CHECK-NEXT: mov v1.h[0], v0.h[1]
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; CHECK-NEXT: mov v0.h[1], v2.h[0]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
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; CHECK-NEXT: ret
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%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec)
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ret {<2 x half>, <2 x half>} %retval
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}
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define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: uzp1 v2.4h, v0.4h, v1.4h
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; CHECK-NEXT: uzp2 v1.4h, v0.4h, v1.4h
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; CHECK-NEXT: fmov d0, d2
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; CHECK-NEXT: ret
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%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec)
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ret {<4 x half>, <4 x half>} %retval
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}
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define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
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; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: uzp2 v1.8h, v0.8h, v1.8h
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec)
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ret {<8 x half>, <8 x half>} %retval
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}
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define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: zip1 v2.2s, v0.2s, v1.2s
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; CHECK-NEXT: zip2 v1.2s, v0.2s, v1.2s
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; CHECK-NEXT: fmov d0, d2
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; CHECK-NEXT: ret
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%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec)
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ret {<2 x float>, <2 x float>} %retval
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}
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define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: uzp2 v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
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ret {<4 x float>, <4 x float>} %retval
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}
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define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
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ret {<2 x double>, <2 x double>} %retval
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}
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; Integers
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define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
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; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.16b, v0.16b, v1.16b
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; CHECK-NEXT: uzp2 v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec)
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ret {<16 x i8>, <16 x i8>} %retval
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}
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define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
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; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: uzp2 v1.8h, v0.8h, v1.8h
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
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ret {<8 x i16>, <8 x i16>} %retval
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}
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define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4i32_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uzp1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: uzp2 v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
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ret {<4 x i32>, <4 x i32>} %retval
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}
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define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
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; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
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ret {<2 x i64>, <2 x i64>} %retval
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}
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; Floating declarations
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declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
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declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
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declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
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declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
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declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
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declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)
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; Integer declarations
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declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
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declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
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declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>)
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declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>)
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