d39b4ce3ce
Using "eabi" for aarch64 targets is a common mistake and warned by Clang Driver. We want to avoid it elsewhere as well. Just use the common "aarch64" without other triple components.
177 lines
6.0 KiB
LLVM
177 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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define <4 x i16> @usra_v4i16(<8 x i8> %0) {
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; CHECK-LABEL: usra_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.8b, v0.8b, #7
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; CHECK-NEXT: usra v0.4h, v0.4h, #7
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; CHECK-NEXT: ret
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%2 = lshr <8 x i8> %0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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%3 = bitcast <8 x i8> %2 to <4 x i16>
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%4 = lshr <4 x i16> %3, <i16 7, i16 7, i16 7, i16 7>
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%5 = or <4 x i16> %4, %3
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ret <4 x i16> %5
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}
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define <4 x i32> @usra_v4i32(<8 x i16> %0) {
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; CHECK-LABEL: usra_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.8h, v0.8h, #15
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; CHECK-NEXT: usra v0.4s, v0.4s, #15
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; CHECK-NEXT: ret
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%2 = lshr <8 x i16> %0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%3 = bitcast <8 x i16> %2 to <4 x i32>
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%4 = lshr <4 x i32> %3, <i32 15, i32 15, i32 15, i32 15>
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%5 = or <4 x i32> %4, %3
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ret <4 x i32> %5
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}
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define <2 x i64> @usra_v2i64(<4 x i32> %0) {
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; CHECK-LABEL: usra_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.4s, v0.4s, #31
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; CHECK-NEXT: usra v0.2d, v0.2d, #31
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; CHECK-NEXT: ret
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%2 = lshr <4 x i32> %0, <i32 31, i32 31, i32 31, i32 31>
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%3 = bitcast <4 x i32> %2 to <2 x i64>
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%4 = lshr <2 x i64> %3, <i64 31, i64 31>
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%5 = or <2 x i64> %4, %3
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ret <2 x i64> %5
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}
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define <1 x i64> @usra_v1i64(<2 x i32> %0) {
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; CHECK-LABEL: usra_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.2s, v0.2s, #31
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; CHECK-NEXT: usra d0, d0, #31
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; CHECK-NEXT: ret
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%2 = lshr <2 x i32> %0, <i32 31, i32 31>
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%3 = bitcast <2 x i32> %2 to <1 x i64>
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%4 = lshr <1 x i64> %3, <i64 31>
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%5 = or <1 x i64> %4, %3
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ret <1 x i64> %5
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}
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define <4 x i16> @ssra_v4i16(<4 x i16> %0) {
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; CHECK-LABEL: ssra_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v1.4h, v0.4h, #15
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; CHECK-NEXT: bic v0.4h, #64, lsl #8
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; CHECK-NEXT: ssra v1.4h, v0.4h, #14
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; CHECK-NEXT: fmov d0, d1
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; CHECK-NEXT: ret
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; set the 15th bit to zero. e.g. 0b1111111111111111 to 0b1011111111111111
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%2 = and <4 x i16> %0, <i16 49151, i16 49151,i16 49151,i16 49151>
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; the first 15 bits are zero, the last bit can be zero or one. e.g. 0b1011111111111111 to 0b0000000000000001
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%3 = lshr <4 x i16> %0, <i16 15, i16 15, i16 15, i16 15>
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; the first 15 bits maybe 1, and the last bit is zero. 0b1011111111111111 to 0b1111111111111110
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%4 = ashr <4 x i16> %2, <i16 14, i16 14, i16 14, i16 14>
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%5 = or <4 x i16> %3, %4
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ret <4 x i16> %5
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}
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define <4 x i32> @ssra_v4i32(<4 x i32> %0) {
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; CHECK-LABEL: ssra_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v1.4s, v0.4s, #31
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; CHECK-NEXT: bic v0.4s, #64, lsl #24
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; CHECK-NEXT: ssra v1.4s, v0.4s, #30
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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; set the 31th bit to zero.
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%2 = and <4 x i32> %0, <i32 3221225471, i32 3221225471,i32 3221225471,i32 3221225471>
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; the first 31 bits are zero, the last bit can be zero or one.
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%3 = lshr <4 x i32> %0, <i32 31, i32 31, i32 31, i32 31>
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; the first 31 bits maybe 1, and the last bit is zero.
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%4 = ashr <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30>
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%5 = or <4 x i32> %3, %4
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ret <4 x i32> %5
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}
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define <1 x i64> @ssra_v1i64(<2 x i32> %0) {
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; CHECK-LABEL: ssra_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr d1, d0, #63
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; CHECK-NEXT: bic v0.2s, #64, lsl #24
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; CHECK-NEXT: ssra d1, d0, #62
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; CHECK-NEXT: fmov d0, d1
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; CHECK-NEXT: ret
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%2 = and <2 x i32> %0, <i32 3221225471, i32 3221225471>
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%3 = bitcast <2 x i32> %2 to <1 x i64>
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%4 = lshr <1 x i64> %3, <i64 63>
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%5 = ashr <1 x i64> %3, <i64 62>
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%6 = or <1 x i64> %4, %5
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ret <1 x i64> %6
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}
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define <2 x i64> @ssra_v2i64(<4 x i32> %0) {
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; CHECK-LABEL: ssra_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v1.2d, v0.2d, #63
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; CHECK-NEXT: bic v0.4s, #64, lsl #24
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; CHECK-NEXT: ssra v1.2d, v0.2d, #62
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%2 = and <4 x i32> %0, <i32 3221225471, i32 3221225471,i32 3221225471,i32 3221225471>
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%3 = bitcast <4 x i32> %2 to <2 x i64>
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%4 = lshr <2 x i64> %3, <i64 63, i64 63>
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%5 = ashr <2 x i64> %3, <i64 62, i64 62>
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%6 = or <2 x i64> %4, %5
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ret <2 x i64> %6
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}
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; Expected to be able to deduce movi is generate a vector of integer
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; and turn USHR+ORR into USRA.
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define <8 x i16> @usra_with_movi_v8i16(<16 x i8> %0, <16 x i8> %1) {
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; CHECK-LABEL: usra_with_movi_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.16b, #1
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; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: usra v0.8h, v0.8h, #7
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; CHECK-NEXT: ret
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%3 = icmp eq <16 x i8> %0, %1
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%4 = zext <16 x i1> %3 to <16 x i8>
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%5 = bitcast <16 x i8> %4 to <8 x i16>
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%6 = lshr <8 x i16> %5, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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%7 = or <8 x i16> %6, %5
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ret <8 x i16> %7
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}
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; Expected to be able to deduce movi is generate a vector of integer
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; and turn USHR+ORR into USRA.
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define <4 x i32> @usra_with_movi_v4i32(<16 x i8> %0, <16 x i8> %1) {
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; CHECK-LABEL: usra_with_movi_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.16b, #1
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; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: usra v0.4s, v0.4s, #15
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; CHECK-NEXT: ret
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%3 = icmp eq <16 x i8> %0, %1
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%4 = zext <16 x i1> %3 to <16 x i8>
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%5 = bitcast <16 x i8> %4 to <4 x i32>
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%6 = lshr <4 x i32> %5, <i32 15, i32 15, i32 15, i32 15>
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%7 = or <4 x i32> %6, %5
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ret <4 x i32> %7
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}
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; Expected to be able to deduce movi is generate a vector of integer
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; and turn USHR+ORR into USRA.
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define <2 x i64> @usra_with_movi_v2i64(<16 x i8> %0, <16 x i8> %1) {
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; CHECK-LABEL: usra_with_movi_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.16b, #1
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; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: usra v0.2d, v0.2d, #31
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; CHECK-NEXT: ret
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%3 = icmp eq <16 x i8> %0, %1
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%4 = zext <16 x i1> %3 to <16 x i8>
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%5 = bitcast <16 x i8> %4 to <2 x i64>
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%6 = lshr <2 x i64> %5, <i64 31, i64 31>
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%7 = or <2 x i64> %6, %5
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ret <2 x i64> %7
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}
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