f2c164c815
SIInsertWaitcnts inserts waitcnt instructions to resolve data dependencies. The GFX10+ vscnt (VMEM store count) counter is never used in this way. It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer. Hence there is no need to conservatively wait for vscnt to be 0 on function entry and before returns. Differential Revision: https://reviews.llvm.org/D153537
104 lines
3.0 KiB
LLVM
104 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX9
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX10
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX11
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define amdgpu_kernel void @test0() {
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; GFX9-LABEL: test0:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test0:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test0:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_endpgm
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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}
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define void @test1() {
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; GFX9-LABEL: test1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test1:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test1:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_endpgm
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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}
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define amdgpu_kernel void @test2(ptr %p, i32 %x) {
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; GFX9-LABEL: test2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_cmp_lt_i32 s2, 1
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; GFX9-NEXT: s_cbranch_scc0 .LBB2_2
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; GFX9-NEXT: ; %bb.1: ; %else
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v2, s2
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: flat_store_dword v[0:1], v2
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .LBB2_2: ; %then
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_cmp_lt_i32 s2, 1
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; GFX10-NEXT: s_cbranch_scc0 .LBB2_2
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; GFX10-NEXT: ; %bb.1: ; %else
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX10-NEXT: v_mov_b32_e32 v2, s2
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: v_mov_b32_e32 v1, s1
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; GFX10-NEXT: flat_store_dword v[0:1], v2
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; GFX10-NEXT: s_endpgm
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; GFX10-NEXT: .LBB2_2: ; %then
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test2:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_cmp_lt_i32 s2, 1
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; GFX11-NEXT: s_cbranch_scc0 .LBB2_2
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; GFX11-NEXT: ; %bb.1: ; %else
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: v_mov_b32_e32 v2, s2
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
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; GFX11-NEXT: flat_store_b32 v[0:1], v2
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; GFX11-NEXT: s_endpgm
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; GFX11-NEXT: .LBB2_2: ; %then
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; GFX11-NEXT: s_endpgm
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%cond = icmp sgt i32 %x, 0
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br i1 %cond, label %then, label %else
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then:
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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else:
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store i32 %x, ptr %p
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ret void
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}
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declare void @llvm.amdgcn.endpgm()
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