e39f6c1844
There are many tests that specify a target triple/CPU flags but no DataLayout which can lead to IR being generated that has unusual behaviour. This commit attempts to use the default DataLayout based on the relevant flags if there is no explicit override on the command line or in the IR file. One thing that is not currently possible to differentiate from a missing datalayout `target datalayout = ""` in the IR file since the current APIs don't allow detecting this case. If it is considered useful to support this case (instead of passing "-data-layout=" on the command line), I can change IR parsers to track whether they have seen such a directive and change the callback type. Differential Revision: https://reviews.llvm.org/D141060
129 lines
7.3 KiB
LLVM
129 lines
7.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -O3 < %s | FileCheck -check-prefix=GCN %s
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s
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; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s
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@a = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
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@b = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
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@c = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
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; FIXME: Should combine the DS instructions into ds_write2 and ds_read2. This
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; does not happen because when SILoadStoreOptimizer is run, the reads and writes
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; are not adjacent. They are only moved later by MachineScheduler.
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define amdgpu_kernel void @no_clobber_ds_load_stores_x2(ptr addrspace(1) %arg, i32 %i) {
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; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x2(
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; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, align 16, !alias.scope !1, !noalias !4
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; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 [[I]]
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; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !alias.scope !1, !noalias !4
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; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 1), align 16, !alias.scope !4, !noalias !1
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; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 1), i32 0, i32 [[I]]
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; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !alias.scope !4, !noalias !1
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; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_A]], [[VAL_B]]
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; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4
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; CHECK-NEXT: ret void
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;
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; GCN-LABEL: no_clobber_ds_load_stores_x2:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GCN-NEXT: v_mov_b32_e32 v0, 1
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v2, 2
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; GCN-NEXT: ds_write_b32 v1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_lshl_b32 s2, s2, 2
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: ds_write_b32 v1, v2 offset:256
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; GCN-NEXT: ds_read_b32 v2, v0
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; GCN-NEXT: ds_read_b32 v0, v0 offset:256
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_u32_e32 v0, v2, v0
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; GCN-NEXT: global_store_dword v1, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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store i32 1, ptr addrspace(3) @a, align 4
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%gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i
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%val.a = load i32, ptr addrspace(3) %gep.a, align 4
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store i32 2, ptr addrspace(3) @b, align 4
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%gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i
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%val.b = load i32, ptr addrspace(3) %gep.b, align 4
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%val = add i32 %val.a, %val.b
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store i32 %val, ptr addrspace(1) %arg, align 4
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ret void
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}
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define amdgpu_kernel void @no_clobber_ds_load_stores_x3(ptr addrspace(1) %arg, i32 %i) {
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; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x3(
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; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, align 16, !alias.scope !6, !noalias !9
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; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 [[I]]
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; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !alias.scope !6, !noalias !9
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; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 1), align 16, !alias.scope !12, !noalias !13
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; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 1), i32 0, i32 [[I]]
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; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !alias.scope !12, !noalias !13
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; CHECK-NEXT: store i32 3, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 2), align 16, !alias.scope !14, !noalias !15
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; CHECK-NEXT: [[GEP_C:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 2), i32 0, i32 [[I]]
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; CHECK-NEXT: [[VAL_C:%.*]] = load i32, ptr addrspace(3) [[GEP_C]], align 4, !alias.scope !14, !noalias !15
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; CHECK-NEXT: [[VAL_1:%.*]] = add i32 [[VAL_A]], [[VAL_B]]
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; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_1]], [[VAL_C]]
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; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4
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; CHECK-NEXT: ret void
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;
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; GCN-LABEL: no_clobber_ds_load_stores_x3:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v2, 2
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; GCN-NEXT: v_mov_b32_e32 v0, 1
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; GCN-NEXT: ds_write_b32 v1, v2 offset:256
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_lshl_b32 s2, s2, 2
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; GCN-NEXT: v_mov_b32_e32 v2, 3
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; GCN-NEXT: ds_write_b32 v1, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: ds_write_b32 v1, v2 offset:512
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; GCN-NEXT: ds_read_b32 v2, v0
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; GCN-NEXT: ds_read_b32 v3, v0 offset:256
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; GCN-NEXT: ds_read_b32 v0, v0 offset:512
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_add_u32_e32 v2, v2, v3
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; GCN-NEXT: v_add_u32_e32 v0, v2, v0
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; GCN-NEXT: global_store_dword v1, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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bb:
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store i32 1, ptr addrspace(3) @a, align 4
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%gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i
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%val.a = load i32, ptr addrspace(3) %gep.a, align 4
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store i32 2, ptr addrspace(3) @b, align 4
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%gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i
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%val.b = load i32, ptr addrspace(3) %gep.b, align 4
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store i32 3, ptr addrspace(3) @c, align 4
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%gep.c = getelementptr inbounds [64 x i32], ptr addrspace(3) @c, i32 0, i32 %i
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%val.c = load i32, ptr addrspace(3) %gep.c, align 4
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%val.1 = add i32 %val.a, %val.b
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%val = add i32 %val.1, %val.c
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store i32 %val, ptr addrspace(1) %arg, align 4
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ret void
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}
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; CHECK: !0 = !{i32 0, i32 1}
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; CHECK: !1 = !{!2}
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; CHECK: !2 = distinct !{!2, !3}
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; CHECK: !3 = distinct !{!3}
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; CHECK: !4 = !{!5}
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; CHECK: !5 = distinct !{!5, !3}
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; CHECK: !6 = !{!7}
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; CHECK: !7 = distinct !{!7, !8}
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; CHECK: !8 = distinct !{!8}
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; CHECK: !9 = !{!10, !11}
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; CHECK: !10 = distinct !{!10, !8}
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; CHECK: !11 = distinct !{!11, !8}
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; CHECK: !12 = !{!10}
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; CHECK: !13 = !{!7, !11}
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; CHECK: !14 = !{!11}
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; CHECK: !15 = !{!7, !10}
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