f7684d8510
Documentation for TargetLowering::getShiftAmountTy says that LegalTypes should generally be true during type legalization, so this patch does that. On AMDGPU the effect is that we use i32 (a sane type) instead of i64 (pointer sized type) for more shift amounts, which in turn allows more formation of rotates and funnel shifts pre-legalization. Differential Revision: https://reviews.llvm.org/D154960
246 lines
9.8 KiB
LLVM
246 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI
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; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI
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; XXX - Why the packing?
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define amdgpu_kernel void @scalar_to_vector_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
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; SI-LABEL: scalar_to_vector_v2i32:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s10, s6
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s8, s2
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; SI-NEXT: s_mov_b32 s9, s3
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; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: v_mov_b32_e32 v1, v0
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v2i32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_mov_b32 s10, s6
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; VI-NEXT: s_mov_b32 s11, s7
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s8, s2
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; VI-NEXT: s_mov_b32 s9, s3
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; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
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; VI-NEXT: v_mov_b32_e32 v1, v0
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; VI-NEXT: s_endpgm
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%tmp1 = load i32, ptr addrspace(1) %in, align 4
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%bc = bitcast i32 %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_kernel void @scalar_to_vector_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
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; SI-LABEL: scalar_to_vector_v2f32:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s10, s6
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s8, s2
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; SI-NEXT: s_mov_b32 s9, s3
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; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: v_mov_b32_e32 v1, v0
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v2f32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_mov_b32 s10, s6
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; VI-NEXT: s_mov_b32 s11, s7
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s8, s2
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; VI-NEXT: s_mov_b32 s9, s3
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; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s1
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
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; VI-NEXT: v_mov_b32_e32 v1, v0
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; VI-NEXT: s_endpgm
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%tmp1 = load float, ptr addrspace(1) %in, align 4
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%bc = bitcast float %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_kernel void @scalar_to_vector_v4i16() {
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; SI-LABEL: scalar_to_vector_v4i16:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
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; SI-NEXT: v_or_b32_e32 v2, v1, v0
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; SI-NEXT: v_and_b32_e32 v1, 0xff00, v2
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
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; SI-NEXT: v_or_b32_e32 v1, v0, v3
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; SI-NEXT: v_or_b32_e32 v0, v2, v3
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v4i16:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v0
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; VI-NEXT: v_or_b32_e32 v2, v1, v0
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; VI-NEXT: v_and_b32_e32 v1, 0xffffff00, v2
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
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; VI-NEXT: v_or_b32_sdwa v1, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: v_or_b32_sdwa v0, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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bb:
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%tmp = load <2 x i8>, ptr addrspace(1) undef, align 1
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%tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
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store <8 x i8> %tmp2, ptr addrspace(1) undef, align 8
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ret void
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}
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define amdgpu_kernel void @scalar_to_vector_v4f16() {
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; SI-LABEL: scalar_to_vector_v4f16:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
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; SI-NEXT: v_or_b32_e32 v2, v1, v0
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; SI-NEXT: v_and_b32_e32 v1, 0xff00, v2
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
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; SI-NEXT: v_or_b32_e32 v1, v0, v3
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; SI-NEXT: v_or_b32_e32 v0, v2, v3
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v4f16:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v0
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; VI-NEXT: v_or_b32_e32 v0, v1, v0
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; VI-NEXT: v_and_b32_e32 v1, 0xffffff00, v0
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; VI-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
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; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
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; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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bb:
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%load = load half, ptr addrspace(1) undef, align 1
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%tmp = bitcast half %load to <2 x i8>
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%tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
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store <8 x i8> %tmp2, ptr addrspace(1) undef, align 8
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ret void
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}
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; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
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; to produce one, but for some reason never made it to selection.
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; define amdgpu_kernel void @scalar_to_vector_test2(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
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; %tmp1 = load i32, ptr addrspace(1) %in, align 4
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; %bc = bitcast i32 %tmp1 to <4 x i8>
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; %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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; store <8 x i8> %tmp2, ptr addrspace(1) %out, align 4
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; ret void
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; }
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; define amdgpu_kernel void @scalar_to_vector_test3(ptr addrspace(1) %out) nounwind {
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; %newvec0 = insertelement <2 x i64> undef, i64 12345, i32 0
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; %newvec1 = insertelement <2 x i64> %newvec0, i64 undef, i32 1
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; %bc = bitcast <2 x i64> %newvec1 to <4 x i32>
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; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4>
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; store <4 x i32> %add, ptr addrspace(1) %out, align 16
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; ret void
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; }
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; define amdgpu_kernel void @scalar_to_vector_test4(ptr addrspace(1) %out) nounwind {
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; %newvec0 = insertelement <4 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <4 x i32> %newvec0 to <8 x i16>
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; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>
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; store <8 x i16> %add, ptr addrspace(1) %out, align 16
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; ret void
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; }
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; define amdgpu_kernel void @scalar_to_vector_test5(ptr addrspace(1) %out) nounwind {
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; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0
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; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>
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; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>
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; store <4 x i16> %add, ptr addrspace(1) %out, align 16
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; ret void
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; }
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define amdgpu_kernel void @scalar_to_vector_test6(ptr addrspace(1) %out, i8 zeroext %val) nounwind {
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; SI-LABEL: scalar_to_vector_test6:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s4, s[0:1], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, s4
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_test6:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dword s4, s[0:1], 0x2c
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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%newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0
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%bc = bitcast <4 x i8> %newvec0 to <2 x half>
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store <2 x half> %bc, ptr addrspace(1) %out
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ret void
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}
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