2eb767c9e1
Scratch instructions are always in addrspace(5), which can only alias with flat (and itself). SMEM and buffer instructions can never reference those address spaces, so they are trivially disjoint.
26 lines
1.1 KiB
LLVM
26 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -o - < %s | FileCheck --check-prefixes=CHECK %s
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define amdgpu_gfx void @example(<4 x i32> inreg %rsrc, ptr addrspace(5) %src, i32 %dst) {
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; CHECK-LABEL: example:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_add_nc_u32_e32 v3, 4, v0
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; CHECK-NEXT: s_clause 0x1
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; CHECK-NEXT: scratch_load_b32 v2, v0, off
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; CHECK-NEXT: scratch_load_b32 v3, v3, off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_store_b64 v[2:3], v1, s[4:7], 0 offen
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x0 = load i32, ptr addrspace(5) %src
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 %x0, <4 x i32> %rsrc, i32 %dst, i32 0, i32 0)
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%src1 = getelementptr i8, ptr addrspace(5) %src, i32 4
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%x1 = load i32, ptr addrspace(5) %src1
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%dst1 = add i32 %dst, 4
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 %x1, <4 x i32> %rsrc, i32 %dst1, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32)
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