f9cd789658
For a future patch, is it important to keep the lowered SGPR spills to be recognized as spill instructions during regalloc. Directly lowering them into V_WRITELANE/V_READLANE won't allow us to attach the SPILL flag to their instructions. This patch introduces the pseudo instructions with the SGPRSpill flag set in their Desc. They will get lowered to equivalent instructions later during post RA pseudo expansion.
127 lines
6.6 KiB
YAML
127 lines
6.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
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# Make sure spill/restore of 320 bit registers works.
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---
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name: spill_restore_sgpr320
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_sgpr320
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; SPILLED: bb.0:
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; SPILLED-NEXT: successors: %bb.1(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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; SPILLED-NEXT: SI_SPILL_S320_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s320) into %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.1:
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; SPILLED-NEXT: successors: %bb.2(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 1
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.2:
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; SPILLED-NEXT: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13 = SI_SPILL_S320_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s320) from %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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;
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; EXPANDED-LABEL: name: spill_restore_sgpr320
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; EXPANDED: bb.0:
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; EXPANDED-NEXT: successors: %bb.1(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, [[DEF]], implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr9, 5, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr10, 6, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr11, 7, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr12, 8, [[DEF]]
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr13, 9, [[DEF]], implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.1:
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; EXPANDED-NEXT: successors: %bb.2(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 1
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.2:
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; EXPANDED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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; EXPANDED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1
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; EXPANDED-NEXT: $sgpr6 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 2
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; EXPANDED-NEXT: $sgpr7 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3
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; EXPANDED-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
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; EXPANDED-NEXT: $sgpr9 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 5
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; EXPANDED-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 6
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; EXPANDED-NEXT: $sgpr11 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 7
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; EXPANDED-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 8
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; EXPANDED-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 9
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; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13
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bb.0:
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S_NOP 0, implicit-def %0:sgpr_320
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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---
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name: spill_restore_vgpr320
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_vgpr320
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; SPILLED: bb.0:
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; SPILLED-NEXT: successors: %bb.1(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
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; SPILLED-NEXT: SI_SPILL_V320_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, %stack.0, $sgpr32, 0, implicit $exec :: (store (s320) into %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.1:
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; SPILLED-NEXT: successors: %bb.2(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 1
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.2:
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; SPILLED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 = SI_SPILL_V320_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s320) from %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
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;
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; EXPANDED-LABEL: name: spill_restore_vgpr320
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; EXPANDED: bb.0:
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; EXPANDED-NEXT: successors: %bb.1(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
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; EXPANDED-NEXT: SI_SPILL_V320_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9, %stack.0, $sgpr32, 0, implicit $exec :: (store (s320) into %stack.0, align 4, addrspace 5)
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; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.1:
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; EXPANDED-NEXT: successors: %bb.2(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 1
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.2:
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; EXPANDED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 = SI_SPILL_V320_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s320) from %stack.0, align 4, addrspace 5)
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; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
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bb.0:
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S_NOP 0, implicit-def %0:vreg_320
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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