5888dee7d0
The ELF code from https://reviews.llvm.org/D112811 emits LDRLIT_ga_pcrel when `TM.isPositionIndependent()` but uses a different condition `Subtarget.isGVIndirectSymbol(GV)` (aka dso_preemptable on ELF targets). This would cause incorrect access for dso_preemptable `__stack_chk_guard` with the static relocation model. Regarding whether `__stack_chk_guard` gets the dso_local specifier, https://reviews.llvm.org/D150841 switched to `M.getDirectAccessExternalData()` (implied by "PIC Level") instead of `TM.getRelocationModel() == Reloc::Static`. The result is that when non-zero "PIC Level" is used with static relocation model (e.g. -fPIE/-fPIC LTO compiles with -no-pie linking), `__stack_chk_guard` accesses are incorrect. ``` ldr r0, .LCPI0_0 ldr r0, [r0] ldr r0, [r0] // incorrectly dereferences __stack_chk_guard ... .LCPI0_0: .long __stack_chk_guard ``` To fix this, for dso_preemptable `__stack_chk_guard`, emit a GOT PIC code sequence like for -fpic using `LDRLIT_ga_pcrel`: ``` ldr r0, .LCPI0_0 .LPC0_0: add r0, pc, r0 ldr r0, [r0] ldr r0, [r0] ... LCPI0_0: .Ltmp0: .long __stack_chk_guard(GOT_PREL)-((.LPC0_0+8)-.Ltmp0) ``` Technically, `LDRLIT_ga_abs` with `R_ARM_GOT_ABS` could be used, but `R_ARM_GOT_ABS` does not have GNU or integrated assembler support. (Note, `.LCPI0_0: .long __stack_chk_guard@GOT` produces an `R_ARM_GOT_BREL`, which is not desired). This patch fixes #6499 while not changing behavior for the following configurations: ``` run arm.linux.nopic --target=arm-linux-gnueabi -fno-pic run arm.linux.pie --target=arm-linux-gnueabi -fpie run arm.linux.pic --target=arm-linux-gnueabi -fpic run armv6.darwin.nopic --target=armv6-apple-darwin -fno-pic run armv6.darwin.dynamicnopic --target=armv6-apple-darwin -mdynamic-no-pic run armv6.darwin.pic --target=armv6-apple-darwin -fpic run armv7.darwin.nopic --target=armv7-apple-darwin -mcpu=cortex-a8 -fno-pic run armv7.darwin.dynamicnopic --target=armv7-apple-darwin -mcpu=cortex-a8 -mdynamic-no-pic run armv7.darwin.pic --target=armv7-apple-darwin -mcpu=cortex-a8 -fpic run arm64.darwin.pic --target=arm64-apple-darwin ```
56 lines
1.7 KiB
LLVM
56 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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;; direct-access-external-data is false due to PIC Level, so __stack_chk_guard
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;; is dso_preemtable. Check that we use GOT PIC code sequence as well because
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;; R_ARM_GOT_ABS does not have assembler support.
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; RUN: llc -relocation-model=static < %s | FileCheck %s
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; RUN: llc -relocation-model=pic < %s | FileCheck %s
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target triple = "armv7a-linux-gnueabi"
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define i32 @test1() #0 {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: sub sp, sp, #8
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; CHECK-NEXT: sub sp, sp, #1024
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; CHECK-NEXT: ldr r0, .LCPI0_0
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; CHECK-NEXT: .LPC0_0:
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; CHECK-NEXT: add r0, pc, r0
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: str r0, [sp, #1028]
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: ldr r0, [sp, #1028]
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; CHECK-NEXT: ldr r1, .LCPI0_1
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; CHECK-NEXT: .LPC0_1:
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; CHECK-NEXT: add r1, pc, r1
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; CHECK-NEXT: ldr r1, [r1]
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; CHECK-NEXT: ldr r1, [r1]
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; CHECK-NEXT: cmp r1, r0
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; CHECK-NEXT: moveq r0, #0
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; CHECK-NEXT: addeq sp, sp, #8
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; CHECK-NEXT: addeq sp, sp, #1024
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; CHECK-NEXT: popeq {r11, pc}
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; CHECK-NEXT: .LBB0_1:
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; CHECK-NEXT: bl __stack_chk_fail
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.2:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: .long __stack_chk_guard(GOT_PREL)-((.LPC0_0+8)-.Ltmp0)
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; CHECK-NEXT: .LCPI0_1:
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; CHECK-NEXT: .Ltmp1:
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; CHECK-NEXT: .long __stack_chk_guard(GOT_PREL)-((.LPC0_1+8)-.Ltmp1)
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%a1 = alloca [256 x i32], align 4
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call void @foo(ptr %a1) #3
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ret i32 0
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}
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declare void @foo(ptr)
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attributes #0 = { nounwind sspstrong }
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!llvm.module.flags = !{!0}
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!0 = !{i32 8, !"PIC Level", i32 2}
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