88ac25b357
Currently MachineCSE forbids PRE when the instruction reads a physical register. Relax this so that it's allowed when the value being read is the same as what would be read in the place the instruction would be hoisted to. This is being done in preparation for adding FPCR handling to the AArch64 backend, in order to prevent it to from worsening the generated code, but for targets that already have a similar register it should improve things. This patch affects code generation in several tests. The new code looks better except for in Thumb2/LowOverheadLoops/memcall.ll where we perform PRE but the LowOverheadLoops transformation then undoes it. Also in AMDGPU/selectcc-opt.ll the CHECK makes things look worse, but actually the function as a whole is better (as a MOV is PRE'd). Differential Revision: https://reviews.llvm.org/D136675
174 lines
4.8 KiB
YAML
174 lines
4.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -run-pass=machine-cse -verify-machineinstrs | FileCheck %s
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--- |
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define void @can_pre() {
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entry:
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br label %for.body
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for.body:
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br i1 undef, label %if.then, label %if.else
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if.then:
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br label %if.end
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if.else:
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br label %if.end
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if.end:
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br label %for.body
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}
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define void @cannot_pre() {
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entry:
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br label %for.body
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for.body:
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br i1 undef, label %if.then, label %if.else
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if.then:
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br label %if.end
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if.else:
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br label %if.end
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if.end:
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br label %for.body
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}
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...
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---
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name: can_pre
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registers:
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- { id: 0, class: f8rc, preferred-register: '' }
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- { id: 1, class: f8rc, preferred-register: '' }
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- { id: 2, class: gprc, preferred-register: '' }
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- { id: 3, class: gprc, preferred-register: '' }
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- { id: 4, class: f8rc, preferred-register: '' }
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- { id: 5, class: f8rc, preferred-register: '' }
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liveins:
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- { reg: '$r1', virtual-reg: '%2' }
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- { reg: '$r2', virtual-reg: '%3' }
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- { reg: '$f1', virtual-reg: '%4' }
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- { reg: '$f2', virtual-reg: '%5' }
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body: |
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; CHECK-LABEL: name: can_pre
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; CHECK: bb.0.for.body:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $r1, $r2, $f1, $f2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:f8rc = COPY $f2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:f8rc = COPY $f1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY $r2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY $r1
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; CHECK-NEXT: $cr0 = CMPLWI [[COPY3]], 0
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; CHECK-NEXT: %6:f8rc = nofpexcept FDIV [[COPY1]], [[COPY]], implicit $rm
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; CHECK-NEXT: BCC 44, $cr0, %bb.1
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.if.then:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: B %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.if.else:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.if.end:
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; CHECK-NEXT: BLR implicit $lr, implicit $rm
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bb.0.for.body:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r1, $r2, $f1, $f2
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%5:f8rc = COPY $f2
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%4:f8rc = COPY $f1
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%3:gprc = COPY $r2
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%2:gprc = COPY $r1
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$cr0 = CMPLWI %2, 0
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BCC 44, $cr0, %bb.1
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B %bb.2
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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%0:f8rc = nofpexcept FDIV %4, %5, implicit $rm
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B %bb.3
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bb.2.if.else:
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successors: %bb.3(0x80000000)
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%1:f8rc = nofpexcept FDIV %4, %5, implicit $rm
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bb.3.if.end:
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BLR implicit $lr, implicit $rm
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...
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---
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name: cannot_pre
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registers:
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- { id: 0, class: f8rc, preferred-register: '' }
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- { id: 1, class: f8rc, preferred-register: '' }
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- { id: 2, class: gprc, preferred-register: '' }
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- { id: 3, class: gprc, preferred-register: '' }
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- { id: 4, class: f8rc, preferred-register: '' }
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- { id: 5, class: f8rc, preferred-register: '' }
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- { id: 6, class: f8rc, preferred-register: '' }
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liveins:
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- { reg: '$r1', virtual-reg: '%2' }
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- { reg: '$r2', virtual-reg: '%3' }
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- { reg: '$f1', virtual-reg: '%4' }
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- { reg: '$f2', virtual-reg: '%5' }
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body: |
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; CHECK-LABEL: name: cannot_pre
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; CHECK: bb.0.for.body:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $r1, $r2, $f1, $f2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:f8rc = COPY $f2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:f8rc = COPY $f1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprc = COPY $r2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY $r1
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; CHECK-NEXT: $cr0 = CMPLWI [[COPY3]], 0
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; CHECK-NEXT: BCC 44, $cr0, %bb.1
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.if.then:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SETRND:%[0-9]+]]:f8rc = SETRND [[COPY2]], implicit-def $rm, implicit $rm
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; CHECK-NEXT: %0:f8rc = nofpexcept FDIV [[COPY1]], [[COPY]], implicit $rm
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; CHECK-NEXT: B %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.if.else:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %1:f8rc = nofpexcept FDIV [[COPY1]], [[COPY]], implicit $rm
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.if.end:
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; CHECK-NEXT: BLR implicit $lr, implicit $rm
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bb.0.for.body:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r1, $r2, $f1, $f2
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%5:f8rc = COPY $f2
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%4:f8rc = COPY $f1
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%3:gprc = COPY $r2
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%2:gprc = COPY $r1
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$cr0 = CMPLWI %2, 0
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BCC 44, $cr0, %bb.1
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B %bb.2
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bb.1.if.then:
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successors: %bb.3(0x80000000)
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%6:f8rc = SETRND %3, implicit-def $rm, implicit $rm
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%0:f8rc = nofpexcept FDIV %4, %5, implicit $rm
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B %bb.3
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bb.2.if.else:
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successors: %bb.3(0x80000000)
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%1:f8rc = nofpexcept FDIV %4, %5, implicit $rm
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bb.3.if.end:
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BLR implicit $lr, implicit $rm
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...
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