8a71f44e00
This doesn't bring us to parity with the test/CodeGen/RISCV/half-* test cases, it simply picks off an initial set that can be supported especially easy. In order to make the review more manageable, I'll follow up with other cases. There is zero innovation in the test cases - they simply take the existing half/float cases and replace f16->bf16 and half->bfloat. Differential Revision: https://reviews.llvm.org/D156895
34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
|
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \
|
|
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFBFMIN %s
|
|
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \
|
|
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFBFMIN %s
|
|
|
|
define bfloat @frem_bf16(bfloat %a, bfloat %b) nounwind {
|
|
; RV32IZFBFMIN-LABEL: frem_bf16:
|
|
; RV32IZFBFMIN: # %bb.0:
|
|
; RV32IZFBFMIN-NEXT: addi sp, sp, -16
|
|
; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
|
; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
|
|
; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa1, fa1
|
|
; RV32IZFBFMIN-NEXT: call fmodf@plt
|
|
; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0
|
|
; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
|
; RV32IZFBFMIN-NEXT: addi sp, sp, 16
|
|
; RV32IZFBFMIN-NEXT: ret
|
|
;
|
|
; RV64IZFBFMIN-LABEL: frem_bf16:
|
|
; RV64IZFBFMIN: # %bb.0:
|
|
; RV64IZFBFMIN-NEXT: addi sp, sp, -16
|
|
; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
|
; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
|
|
; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa1, fa1
|
|
; RV64IZFBFMIN-NEXT: call fmodf@plt
|
|
; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0
|
|
; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
|
; RV64IZFBFMIN-NEXT: addi sp, sp, 16
|
|
; RV64IZFBFMIN-NEXT: ret
|
|
%1 = frem bfloat %a, %b
|
|
ret bfloat %1
|
|
}
|