cbdccb30c2
If a virtual register is not assigned preferred physical register, it means some COPY instructions will be changed to real register move instructions. In this case we can try to split the virtual register in colder blocks, if success, the original COPY instructions can be deleted, and the new COPY instructions in colder blocks will be generated as register move instructions. It results in fewer dynamic register move instructions executed. The new test case split-reg-with-hint.ll gives an example, the hot path contains 24 instructions without this patch, now it is only 4 instructions with this patch. Differential Revision: https://reviews.llvm.org/D156491
131 lines
5.0 KiB
LLVM
131 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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; RUN: llc -mtriple=riscv32 -mattr=+zdinx -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zdinx -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
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define double @func(double %d, i32 %n) nounwind {
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; RV32IFD-LABEL: func:
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; RV32IFD: # %bb.0: # %entry
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; RV32IFD-NEXT: addi sp, sp, -32
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; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: sw a0, 16(sp)
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; RV32IFD-NEXT: sw a1, 20(sp)
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; RV32IFD-NEXT: fld fa5, 16(sp)
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; RV32IFD-NEXT: beqz a2, .LBB0_2
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; RV32IFD-NEXT: # %bb.1: # %if.else
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; RV32IFD-NEXT: addi a2, a2, -1
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; RV32IFD-NEXT: fsd fa5, 16(sp)
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; RV32IFD-NEXT: lw a0, 16(sp)
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; RV32IFD-NEXT: lw a1, 20(sp)
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; RV32IFD-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
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; RV32IFD-NEXT: call func@plt
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; RV32IFD-NEXT: sw a0, 16(sp)
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; RV32IFD-NEXT: sw a1, 20(sp)
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; RV32IFD-NEXT: fld fa5, 16(sp)
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; RV32IFD-NEXT: fld fa4, 8(sp) # 8-byte Folded Reload
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; RV32IFD-NEXT: fadd.d fa5, fa5, fa4
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; RV32IFD-NEXT: .LBB0_2: # %return
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; RV32IFD-NEXT: fsd fa5, 16(sp)
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; RV32IFD-NEXT: lw a0, 16(sp)
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; RV32IFD-NEXT: lw a1, 20(sp)
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; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32IFD-NEXT: addi sp, sp, 32
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: func:
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; RV64IFD: # %bb.0: # %entry
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; RV64IFD-NEXT: sext.w a2, a1
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; RV64IFD-NEXT: fmv.d.x fa5, a0
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; RV64IFD-NEXT: beqz a2, .LBB0_2
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; RV64IFD-NEXT: # %bb.1: # %if.else
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; RV64IFD-NEXT: addi sp, sp, -16
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; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: addiw a1, a1, -1
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; RV64IFD-NEXT: fmv.x.d a0, fa5
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; RV64IFD-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
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; RV64IFD-NEXT: call func@plt
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; RV64IFD-NEXT: fmv.d.x fa5, a0
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; RV64IFD-NEXT: fld fa4, 0(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: fadd.d fa5, fa5, fa4
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; RV64IFD-NEXT: fmv.x.d a0, fa5
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; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IFD-NEXT: addi sp, sp, 16
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; RV64IFD-NEXT: ret
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; RV64IFD-NEXT: .LBB0_2: # %return
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; RV64IFD-NEXT: fmv.x.d a0, fa5
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; RV64IFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: func:
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; RV32IZFINXZDINX: # %bb.0: # %entry
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
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; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
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; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw s0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw s1, 12(sp)
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; RV32IZFINXZDINX-NEXT: beqz a2, .LBB0_2
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; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else
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; RV32IZFINXZDINX-NEXT: addi a2, a2, -1
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; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: call func@plt
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: j .LBB0_3
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; RV32IZFINXZDINX-NEXT: .LBB0_2: # %return
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; RV32IZFINXZDINX-NEXT: sw s0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
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; RV32IZFINXZDINX-NEXT: .LBB0_3: # %return
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
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; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
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; RV32IZFINXZDINX-NEXT: ret
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;
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; RV64IZFINXZDINX-LABEL: func:
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; RV64IZFINXZDINX: # %bb.0: # %entry
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; RV64IZFINXZDINX-NEXT: sext.w a2, a1
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; RV64IZFINXZDINX-NEXT: beqz a2, .LBB0_2
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; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.else
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; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFINXZDINX-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
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; RV64IZFINXZDINX-NEXT: addiw a1, a1, -1
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; RV64IZFINXZDINX-NEXT: mv s0, a0
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; RV64IZFINXZDINX-NEXT: call func@plt
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; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, s0
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; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFINXZDINX-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
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; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
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; RV64IZFINXZDINX-NEXT: .LBB0_2: # %return
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; RV64IZFINXZDINX-NEXT: ret
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entry:
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%cmp = icmp eq i32 %n, 0
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br i1 %cmp, label %return, label %if.else
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if.else:
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%sub = add i32 %n, -1
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%call = tail call double @func(double %d, i32 %sub)
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%add = fadd double %call, %d
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ret double %add
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return:
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ret double %d
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}
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