86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
260 lines
7.0 KiB
LLVM
260 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32ZBB
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64ZBB
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declare i32 @llvm.abs.i32(i32, i1 immarg)
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declare i64 @llvm.abs.i64(i64, i1 immarg)
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define i32 @neg_abs32(i32 %x) {
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; RV32I-LABEL: neg_abs32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: neg_abs32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: neg a1, a0
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; RV32ZBB-NEXT: min a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: neg_abs32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a1, a0, 31
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: subw a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: neg_abs32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: sraiw a1, a0, 31
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; RV64ZBB-NEXT: xor a0, a0, a1
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; RV64ZBB-NEXT: subw a0, a1, a0
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; RV64ZBB-NEXT: ret
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%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
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%neg = sub nsw i32 0, %abs
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ret i32 %neg
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}
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define i32 @select_neg_abs32(i32 %x) {
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; RV32I-LABEL: select_neg_abs32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: select_neg_abs32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: neg a1, a0
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; RV32ZBB-NEXT: min a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: select_neg_abs32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a1, a0, 31
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: subw a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: select_neg_abs32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: sraiw a1, a0, 31
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; RV64ZBB-NEXT: xor a0, a0, a1
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; RV64ZBB-NEXT: subw a0, a1, a0
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; RV64ZBB-NEXT: ret
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%1 = icmp slt i32 %x, 0
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%2 = sub nsw i32 0, %x
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%3 = select i1 %1, i32 %x, i32 %2
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ret i32 %3
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}
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define i64 @neg_abs64(i64 %x) {
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; RV32I-LABEL: neg_abs64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a2, a1, 31
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: sltu a3, a2, a0
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: sub a1, a2, a1
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: neg_abs64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: srai a2, a1, 31
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; RV32ZBB-NEXT: xor a0, a0, a2
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; RV32ZBB-NEXT: sltu a3, a2, a0
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; RV32ZBB-NEXT: xor a1, a1, a2
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; RV32ZBB-NEXT: sub a1, a2, a1
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; RV32ZBB-NEXT: sub a1, a1, a3
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; RV32ZBB-NEXT: sub a0, a2, a0
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: neg_abs64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a1, a0, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: neg_abs64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: neg a1, a0
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; RV64ZBB-NEXT: min a0, a0, a1
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; RV64ZBB-NEXT: ret
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%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
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%neg = sub nsw i64 0, %abs
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ret i64 %neg
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}
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define i64 @select_neg_abs64(i64 %x) {
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; RV32I-LABEL: select_neg_abs64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a2, a1, 31
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: sltu a3, a2, a0
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: sub a1, a2, a1
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: select_neg_abs64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: srai a2, a1, 31
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; RV32ZBB-NEXT: xor a0, a0, a2
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; RV32ZBB-NEXT: sltu a3, a2, a0
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; RV32ZBB-NEXT: xor a1, a1, a2
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; RV32ZBB-NEXT: sub a1, a2, a1
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; RV32ZBB-NEXT: sub a1, a1, a3
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; RV32ZBB-NEXT: sub a0, a2, a0
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: select_neg_abs64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a1, a0, 63
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: select_neg_abs64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: neg a1, a0
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; RV64ZBB-NEXT: min a0, a0, a1
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; RV64ZBB-NEXT: ret
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%1 = icmp slt i64 %x, 0
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%2 = sub nsw i64 0, %x
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%3 = select i1 %1, i64 %x, i64 %2
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ret i64 %3
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}
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define i32 @neg_abs32_multiuse(i32 %x, ptr %y) {
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; RV32I-LABEL: neg_abs32_multiuse:
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a2, a0, 31
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: sub a2, a0, a2
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; RV32I-NEXT: neg a0, a2
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; RV32I-NEXT: sw a2, 0(a1)
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: neg_abs32_multiuse:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: neg a2, a0
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; RV32ZBB-NEXT: max a2, a0, a2
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; RV32ZBB-NEXT: neg a0, a2
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; RV32ZBB-NEXT: sw a2, 0(a1)
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: neg_abs32_multiuse:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sraiw a2, a0, 31
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; RV64I-NEXT: xor a0, a0, a2
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; RV64I-NEXT: subw a2, a0, a2
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; RV64I-NEXT: negw a0, a2
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; RV64I-NEXT: sw a2, 0(a1)
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: neg_abs32_multiuse:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: sext.w a0, a0
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; RV64ZBB-NEXT: negw a2, a0
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; RV64ZBB-NEXT: max a2, a0, a2
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; RV64ZBB-NEXT: negw a0, a2
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; RV64ZBB-NEXT: sw a2, 0(a1)
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; RV64ZBB-NEXT: ret
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%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
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store i32 %abs, ptr %y
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%neg = sub nsw i32 0, %abs
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ret i32 %neg
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}
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define i64 @neg_abs64_multiuse(i64 %x, ptr %y) {
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; RV32I-LABEL: neg_abs64_multiuse:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bgez a1, .LBB5_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: snez a3, a0
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; RV32I-NEXT: neg a1, a1
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: neg a0, a0
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; RV32I-NEXT: .LBB5_2:
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; RV32I-NEXT: sw a0, 0(a2)
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; RV32I-NEXT: snez a3, a0
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; RV32I-NEXT: neg a4, a1
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; RV32I-NEXT: sub a3, a4, a3
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; RV32I-NEXT: neg a0, a0
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; RV32I-NEXT: sw a1, 4(a2)
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: neg_abs64_multiuse:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: bgez a1, .LBB5_2
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; RV32ZBB-NEXT: # %bb.1:
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; RV32ZBB-NEXT: snez a3, a0
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; RV32ZBB-NEXT: neg a1, a1
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; RV32ZBB-NEXT: sub a1, a1, a3
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; RV32ZBB-NEXT: neg a0, a0
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; RV32ZBB-NEXT: .LBB5_2:
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; RV32ZBB-NEXT: sw a0, 0(a2)
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; RV32ZBB-NEXT: snez a3, a0
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; RV32ZBB-NEXT: neg a4, a1
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; RV32ZBB-NEXT: sub a3, a4, a3
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; RV32ZBB-NEXT: neg a0, a0
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; RV32ZBB-NEXT: sw a1, 4(a2)
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; RV32ZBB-NEXT: mv a1, a3
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; RV32ZBB-NEXT: ret
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;
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; RV64I-LABEL: neg_abs64_multiuse:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srai a2, a0, 63
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; RV64I-NEXT: xor a0, a0, a2
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; RV64I-NEXT: sub a2, a0, a2
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; RV64I-NEXT: neg a0, a2
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; RV64I-NEXT: sd a2, 0(a1)
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: neg_abs64_multiuse:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: neg a2, a0
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; RV64ZBB-NEXT: max a2, a0, a2
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; RV64ZBB-NEXT: neg a0, a2
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; RV64ZBB-NEXT: sd a2, 0(a1)
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; RV64ZBB-NEXT: ret
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%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
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store i64 %abs, ptr %y
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%neg = sub nsw i64 0, %abs
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ret i64 %neg
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}
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