ffb2af3ed6
LSR uses SCEVExpander to generate induction formulas. The expander internally tries to reuse existing IR expressions. To do that, it needs to strip any poison generating flags (nsw, nuw, exact, nneg, etc..) which may not be valid for the newly added users. This is conservatively correct, but has the effect that LSR will strip nneg flags on zext instructions involved in trip counts in loop preheaders. To avoid this, this patch adjusts the expanded to reinfer the flags on the CSE candidate if legal for all possible users. This should fix the regression reported in https://github.com/llvm/llvm-project/issues/71200. This should arguably be done inside canReuseInstruction instead, but doing it outside is more conservative compile time wise. Both canReuseInstruction and isGuaranteedNotToBePoison walk operand lists, so right now we are performing work which is roughly O(N^2) in the size of the operand graph. We should fix that before making the per operand step more expensive. My tenative plan is to land this, and then rework the code to sink the logic into more core interfaces.
130 lines
5.2 KiB
LLVM
130 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
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; Make sure we don't emit a pair of shift for the zext in the preheader. We
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; can tell that bit 31 is 0 in the preheader and rely on %n already being
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; sign extended without adding zeros explicitly.
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define void @test1(ptr nocapture noundef %a, i32 noundef signext %n) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: blez a1, .LBB0_3
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: slli a1, a1, 2
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; CHECK-NEXT: add a1, a0, a1
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; CHECK-NEXT: .LBB0_2: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lw a2, 0(a0)
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; CHECK-NEXT: addi a2, a2, 4
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; CHECK-NEXT: sw a2, 0(a0)
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; CHECK-NEXT: addi a0, a0, 4
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; CHECK-NEXT: bne a0, a1, .LBB0_2
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; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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%cmp3 = icmp sgt i32 %n, 0
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br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext nneg i32 %n to i64
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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%0 = load i32, ptr %arrayidx, align 4
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%add = add nsw i32 %0, 4
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store i32 %add, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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; Make sure we convert the 4294967294 in for.body.preheader.new to -2 based on
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; the upper 33 bits being zero by the dominating condition %cmp3.
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define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: blez a1, .LBB1_7
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: li a3, 1
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; CHECK-NEXT: andi a2, a1, 1
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; CHECK-NEXT: bne a1, a3, .LBB1_3
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: li a3, 0
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; CHECK-NEXT: j .LBB1_5
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; CHECK-NEXT: .LBB1_3: # %for.body.preheader.new
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; CHECK-NEXT: li a3, 0
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; CHECK-NEXT: andi a1, a1, -2
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; CHECK-NEXT: addi a4, a0, 4
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; CHECK-NEXT: .LBB1_4: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lw a5, -4(a4)
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; CHECK-NEXT: lw a6, 0(a4)
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; CHECK-NEXT: addi a5, a5, 4
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; CHECK-NEXT: sw a5, -4(a4)
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; CHECK-NEXT: addi a6, a6, 4
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; CHECK-NEXT: sw a6, 0(a4)
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; CHECK-NEXT: addi a3, a3, 2
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; CHECK-NEXT: addi a4, a4, 8
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; CHECK-NEXT: bne a1, a3, .LBB1_4
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; CHECK-NEXT: .LBB1_5: # %for.cond.cleanup.loopexit.unr-lcssa
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; CHECK-NEXT: beqz a2, .LBB1_7
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; CHECK-NEXT: # %bb.6: # %for.body.epil
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; CHECK-NEXT: slli a3, a3, 2
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; CHECK-NEXT: add a0, a0, a3
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: addi a1, a1, 4
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: .LBB1_7: # %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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%cmp3 = icmp sgt i32 %n, 0
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br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext nneg i32 %n to i64
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%xtraiter = and i64 %wide.trip.count, 1
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%0 = icmp eq i32 %n, 1
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br i1 %0, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new
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for.body.preheader.new: ; preds = %for.body.preheader
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%unroll_iter = and i64 %wide.trip.count, 4294967294
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br label %for.body
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for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body.preheader
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%indvars.iv.unr = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next.1, %for.body ]
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%lcmp.mod.not = icmp eq i64 %xtraiter, 0
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br i1 %lcmp.mod.not, label %for.cond.cleanup, label %for.body.epil
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for.body.epil: ; preds = %for.cond.cleanup.loopexit.unr-lcssa
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%arrayidx.epil = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.unr
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%1 = load i32, ptr %arrayidx.epil, align 4
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%add.epil = add nsw i32 %1, 4
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store i32 %add.epil, ptr %arrayidx.epil, align 4
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.body.epil, %for.cond.cleanup.loopexit.unr-lcssa, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.preheader.new
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%indvars.iv = phi i64 [ 0, %for.body.preheader.new ], [ %indvars.iv.next.1, %for.body ]
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%niter = phi i64 [ 0, %for.body.preheader.new ], [ %niter.next.1, %for.body ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
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%2 = load i32, ptr %arrayidx, align 4
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%add = add nsw i32 %2, 4
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store i32 %add, ptr %arrayidx, align 4
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%indvars.iv.next = or disjoint i64 %indvars.iv, 1
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%arrayidx.1 = getelementptr inbounds i32, ptr %a, i64 %indvars.iv.next
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%3 = load i32, ptr %arrayidx.1, align 4
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%add.1 = add nsw i32 %3, 4
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store i32 %add.1, ptr %arrayidx.1, align 4
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%indvars.iv.next.1 = add nuw nsw i64 %indvars.iv, 2
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%niter.next.1 = add i64 %niter, 2
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%niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
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br i1 %niter.ncmp.1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body
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}
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