eb44f3fc58
This improves our coverage of soft float libcalls lowering. Remove most of the test cases from rv64i-single-softfloat.ll. They were duplicated in the test files that now test softflow. Only a couple test cases for constrained FP remain. Those should be removed when we start supporting constrained FP. This is follow up from D113528.
59 lines
2.1 KiB
LLVM
59 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; The test cases check that we use the si versions of the conversions from
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; double.
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declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
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declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
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define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
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; RV64I-LABEL: strict_fp64_to_ui32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __fixunsdfsi@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IF-LABEL: strict_fp64_to_ui32:
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; RV64IF: # %bb.0: # %entry
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call __fixunsdfsi@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
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ret i32 %conv
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}
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define i32 @strict_fp64_to_si32(double %a) nounwind strictfp {
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; RV64I-LABEL: strict_fp64_to_si32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64I-NEXT: call __fixdfsi@plt
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; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IF-LABEL: strict_fp64_to_si32:
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; RV64IF: # %bb.0: # %entry
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; RV64IF-NEXT: addi sp, sp, -16
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; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IF-NEXT: call __fixdfsi@plt
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; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IF-NEXT: addi sp, sp, 16
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; RV64IF-NEXT: ret
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
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ret i32 %conv
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}
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