5fdab3c81b
Like what has been done in AArch64 (D125335). We enable this under `-O2` to show the codegen diffs here but we may only do this under `-O3` like AArch64. There are two cases that we may produce these eliminable copies: 1. ISel of `FrameIndex`. Like `rvv/fixed-vectors-calling-conv.ll`. 2. Tail duplication. Like `select-optimize-multiple.ll`. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D144535
292 lines
8.1 KiB
LLVM
292 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32,RV32I
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64,RV64I
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32,RV32IZbb
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64,RV64IZbb
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declare i4 @llvm.sadd.sat.i4(i4, i4)
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declare i8 @llvm.sadd.sat.i8(i8, i8)
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
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; RV32-LABEL: func:
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; RV32: # %bb.0:
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; RV32-NEXT: mv a2, a0
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: slt a2, a0, a2
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; RV32-NEXT: slti a1, a1, 0
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; RV32-NEXT: beq a1, a2, .LBB0_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: srai a0, a0, 31
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; RV32-NEXT: lui a1, 524288
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: .LBB0_2:
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; RV32-NEXT: ret
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;
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; RV64I-LABEL: func:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: addiw a2, a1, -1
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; RV64I-NEXT: bge a0, a2, .LBB0_3
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: bge a1, a0, .LBB0_4
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; RV64I-NEXT: .LBB0_2:
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB0_3:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: blt a1, a2, .LBB0_2
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; RV64I-NEXT: .LBB0_4:
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; RV64I-NEXT: lui a0, 524288
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; RV64I-NEXT: ret
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;
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; RV64IZbb-LABEL: func:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: add a0, a0, a1
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; RV64IZbb-NEXT: lui a1, 524288
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; RV64IZbb-NEXT: addiw a2, a1, -1
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; RV64IZbb-NEXT: min a0, a0, a2
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; RV64IZbb-NEXT: max a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
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ret i32 %tmp;
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: func2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a4, a1
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: add a5, a4, a3
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sltu a1, a0, a1
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; RV32I-NEXT: add a1, a5, a1
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; RV32I-NEXT: xor a2, a4, a1
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; RV32I-NEXT: xor a3, a4, a3
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; RV32I-NEXT: not a3, a3
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; RV32I-NEXT: and a2, a3, a2
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; RV32I-NEXT: bgez a2, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srai a0, a1, 31
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a1, a0, a1
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: ret
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;
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; RV64-LABEL: func2:
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; RV64: # %bb.0:
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; RV64-NEXT: mv a2, a0
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: slt a2, a0, a2
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; RV64-NEXT: slti a1, a1, 0
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; RV64-NEXT: beq a1, a2, .LBB1_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: srai a0, a0, 63
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; RV64-NEXT: li a1, -1
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; RV64-NEXT: slli a1, a1, 63
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: .LBB1_2:
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; RV64-NEXT: ret
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;
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; RV32IZbb-LABEL: func2:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: mv a4, a1
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; RV32IZbb-NEXT: mv a1, a0
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; RV32IZbb-NEXT: add a5, a4, a3
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; RV32IZbb-NEXT: add a0, a0, a2
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; RV32IZbb-NEXT: sltu a1, a0, a1
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; RV32IZbb-NEXT: add a1, a5, a1
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; RV32IZbb-NEXT: xor a2, a4, a1
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; RV32IZbb-NEXT: xor a3, a4, a3
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; RV32IZbb-NEXT: andn a2, a2, a3
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; RV32IZbb-NEXT: bgez a2, .LBB1_2
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; RV32IZbb-NEXT: # %bb.1:
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; RV32IZbb-NEXT: srai a0, a1, 31
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; RV32IZbb-NEXT: lui a1, 524288
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; RV32IZbb-NEXT: xor a1, a0, a1
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; RV32IZbb-NEXT: .LBB1_2:
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; RV32IZbb-NEXT: ret
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%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
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ret i64 %tmp;
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}
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define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
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; RV32I-LABEL: func16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lui a1, 8
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: bge a0, a1, .LBB2_3
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: lui a1, 1048568
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; RV32I-NEXT: bge a1, a0, .LBB2_4
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB2_3:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: lui a1, 1048568
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; RV32I-NEXT: blt a1, a0, .LBB2_2
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; RV32I-NEXT: .LBB2_4:
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; RV32I-NEXT: lui a0, 1048568
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: lui a1, 8
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; RV64I-NEXT: addiw a1, a1, -1
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; RV64I-NEXT: bge a0, a1, .LBB2_3
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: lui a1, 1048568
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; RV64I-NEXT: bge a1, a0, .LBB2_4
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; RV64I-NEXT: .LBB2_2:
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB2_3:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: lui a1, 1048568
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; RV64I-NEXT: blt a1, a0, .LBB2_2
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; RV64I-NEXT: .LBB2_4:
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; RV64I-NEXT: lui a0, 1048568
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func16:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: add a0, a0, a1
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; RV32IZbb-NEXT: lui a1, 8
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; RV32IZbb-NEXT: addi a1, a1, -1
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; RV32IZbb-NEXT: min a0, a0, a1
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; RV32IZbb-NEXT: lui a1, 1048568
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; RV32IZbb-NEXT: max a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func16:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: add a0, a0, a1
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; RV64IZbb-NEXT: lui a1, 8
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; RV64IZbb-NEXT: addiw a1, a1, -1
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; RV64IZbb-NEXT: min a0, a0, a1
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; RV64IZbb-NEXT: lui a1, 1048568
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; RV64IZbb-NEXT: max a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
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; RV32I-LABEL: func8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: li a1, 127
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; RV32I-NEXT: bge a0, a1, .LBB3_3
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a1, -128
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; RV32I-NEXT: bge a1, a0, .LBB3_4
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB3_3:
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; RV32I-NEXT: li a0, 127
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; RV32I-NEXT: li a1, -128
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; RV32I-NEXT: blt a1, a0, .LBB3_2
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; RV32I-NEXT: .LBB3_4:
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; RV32I-NEXT: li a0, -128
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: li a1, 127
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; RV64I-NEXT: bge a0, a1, .LBB3_3
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a1, -128
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; RV64I-NEXT: bge a1, a0, .LBB3_4
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; RV64I-NEXT: .LBB3_2:
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB3_3:
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; RV64I-NEXT: li a0, 127
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; RV64I-NEXT: li a1, -128
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; RV64I-NEXT: blt a1, a0, .LBB3_2
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; RV64I-NEXT: .LBB3_4:
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; RV64I-NEXT: li a0, -128
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func8:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: add a0, a0, a1
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; RV32IZbb-NEXT: li a1, 127
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; RV32IZbb-NEXT: min a0, a0, a1
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; RV32IZbb-NEXT: li a1, -128
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; RV32IZbb-NEXT: max a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func8:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: add a0, a0, a1
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; RV64IZbb-NEXT: li a1, 127
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; RV64IZbb-NEXT: min a0, a0, a1
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; RV64IZbb-NEXT: li a1, -128
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; RV64IZbb-NEXT: max a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
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; RV32I-LABEL: func3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: li a1, 7
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; RV32I-NEXT: bge a0, a1, .LBB4_3
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a1, -8
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; RV32I-NEXT: bge a1, a0, .LBB4_4
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB4_3:
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; RV32I-NEXT: li a0, 7
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; RV32I-NEXT: li a1, -8
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; RV32I-NEXT: blt a1, a0, .LBB4_2
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; RV32I-NEXT: .LBB4_4:
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; RV32I-NEXT: li a0, -8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: li a1, 7
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; RV64I-NEXT: bge a0, a1, .LBB4_3
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a1, -8
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; RV64I-NEXT: bge a1, a0, .LBB4_4
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB4_3:
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; RV64I-NEXT: li a0, 7
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; RV64I-NEXT: li a1, -8
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; RV64I-NEXT: blt a1, a0, .LBB4_2
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; RV64I-NEXT: .LBB4_4:
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; RV64I-NEXT: li a0, -8
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func3:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: add a0, a0, a1
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; RV32IZbb-NEXT: li a1, 7
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; RV32IZbb-NEXT: min a0, a0, a1
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; RV32IZbb-NEXT: li a1, -8
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; RV32IZbb-NEXT: max a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func3:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: add a0, a0, a1
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; RV64IZbb-NEXT: li a1, 7
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; RV64IZbb-NEXT: min a0, a0, a1
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; RV64IZbb-NEXT: li a1, -8
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; RV64IZbb-NEXT: max a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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}
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