b9208aca9b
There are no 64-bit variants of these ALU / SETHI instructions in V9. Remove these instruction definitions and add patterns to match DAG nodes to the generic instructions defined in SparcInstrInfo.td. This is not strictly NFC because of the changes in `2011-01-11-FrameAddr.ll` test. The reason is that Sparc delay slot filler pass handled ADDrr but not ADDXrr, which are now the same instruction.
117 lines
2.6 KiB
LLVM
117 lines
2.6 KiB
LLVM
;RUN: llc -march=sparc -show-mc-encoding < %s | FileCheck %s -check-prefix=V8
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;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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;RUN: llc -march=sparc -show-mc-encoding -regalloc=basic < %s | FileCheck %s -check-prefix=V8
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;RUN: llc -march=sparc -regalloc=basic -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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;RUN: llc -march=sparcv9 < %s | FileCheck %s -check-prefix=SPARC64
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define i8* @frameaddr() nounwind readnone {
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entry:
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;V8-LABEL: frameaddr:
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;V8: save %sp, -96, %sp
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;V8: ret
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;V8: restore %g0, %fp, %o0
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;V9-LABEL: frameaddr:
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;V9: save %sp, -96, %sp
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;V9: ret
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;V9: restore %g0, %fp, %o0
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;SPARC64-LABEL: frameaddr
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;SPARC64: save %sp, -128, %sp
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;SPARC64: ret
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;SPARC64: restore %fp, 2047, %o0
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%0 = tail call i8* @llvm.frameaddress(i32 0)
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ret i8* %0
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}
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define i8* @frameaddr2() nounwind readnone {
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entry:
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;V8-LABEL: frameaddr2:
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;V8: ta 3 ! encoding: [0x91,0xd0,0x20,0x03]
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;V8: ld [%fp+56], {{.+}}
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;V8: ld [{{.+}}+56], {{.+}}
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;V8: ld [{{.+}}+56], {{.+}}
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;V9-LABEL: frameaddr2:
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;V9: flushw
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;V9: ld [%fp+56], {{.+}}
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;V9: ld [{{.+}}+56], {{.+}}
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;V9: ld [{{.+}}+56], {{.+}}
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;SPARC64-LABEL: frameaddr2
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;SPARC64: flushw
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;SPARC64: ldx [%fp+2159], %[[R0:[goli][0-7]]]
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;SPARC64: ldx [%[[R0]]+2159], %[[R1:[goli][0-7]]]
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;SPARC64: ldx [%[[R1]]+2159], %[[R2:[goli][0-7]]]
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;SPARC64: ret
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;SPARC64: restore %[[R2]], 2047, %o0
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%0 = tail call i8* @llvm.frameaddress(i32 3)
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ret i8* %0
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}
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declare i8* @llvm.frameaddress(i32) nounwind readnone
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define i8* @retaddr() nounwind readnone {
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entry:
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;V8-LABEL: retaddr:
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;V8: mov %o7, {{.+}}
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;V9-LABEL: retaddr:
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;V9: mov %o7, {{.+}}
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;SPARC64-LABEL: retaddr
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;SPARC64: mov %o7, {{.+}}
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%0 = tail call i8* @llvm.returnaddress(i32 0)
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ret i8* %0
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}
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define i8* @retaddr2() nounwind readnone {
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entry:
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;V8-LABEL: retaddr2:
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;V8: ta 3
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;V8: ld [%fp+56], {{.+}}
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;V8: ld [{{.+}}+56], {{.+}}
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;V8: ld [{{.+}}+60], {{.+}}
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;V9-LABEL: retaddr2:
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;V9: flushw
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;V9: ld [%fp+56], {{.+}}
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;V9: ld [{{.+}}+56], {{.+}}
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;V9: ld [{{.+}}+60], {{.+}}
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;SPARC64-LABEL: retaddr2
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;SPARC64: flushw
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;SPARC64: ldx [%fp+2159], %[[R0:[goli][0-7]]]
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;SPARC64: ldx [%[[R0]]+2159], %[[R1:[goli][0-7]]]
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;SPARC64: ldx [%[[R1]]+2167], {{.+}}
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%0 = tail call i8* @llvm.returnaddress(i32 3)
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ret i8* %0
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}
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define i8* @retaddr3() nounwind readnone {
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entry:
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;V8-LABEL: retaddr3:
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;V8: ta 3
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;V8: ld [%fp+60], {{.+}}
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;V9-LABEL: retaddr3:
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;V9: flushw
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;V9: ld [%fp+60], {{.+}}
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;SPARC64-LABEL: retaddr3
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;SPARC64: flushw
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;SPARC64: ldx [%fp+2167], %[[R0:[goli][0-7]]]
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%0 = tail call i8* @llvm.returnaddress(i32 1)
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ret i8* %0
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}
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declare i8* @llvm.returnaddress(i32) nounwind readnone
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