8bfb2b6d77
IRTranslator lowers switches to [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. Since values and destination MBBs are included in the spv_switch intrinsics, the sequences are not needed for ISel. Before this commit, the information decoded by these sequences were added to spv_switch intrinsics in SPIRVPreLegalizer and the sequences were kept until SPIRVModuleAnalysis where they were marked skipped for emission. After this commit, the [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences and MBBs containing only these MIs are erased in SPIRVPreLegalizer. Differential Revision: https://reviews.llvm.org/D146923
52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
;; __kernel void test_switch(__global int* res, uchar val)
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;; {
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;; switch(val)
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;; {
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;; case 0:
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;; *res = 1;
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;; break;
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;; case 1:
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;; *res = 2;
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;; break;
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;; case 2:
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;; *res = 3;
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;; break;
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;; }
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;; }
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; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; CHECK-SPIRV: OpSwitch %[[#]] %[[#]] 0 %[[#]] 1 %[[#]] 2 %[[#]]
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define spir_kernel void @test_switch(i32 addrspace(1)* %res, i8 zeroext %val) {
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entry:
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%res.addr = alloca i32 addrspace(1)*, align 4
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%val.addr = alloca i8, align 1
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store i32 addrspace(1)* %res, i32 addrspace(1)** %res.addr, align 4
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store i8 %val, i8* %val.addr, align 1
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%0 = load i8, i8* %val.addr, align 1
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switch i8 %0, label %sw.epilog [
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i8 0, label %sw.bb
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i8 1, label %sw.bb1
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i8 2, label %sw.bb2
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]
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sw.bb: ; preds = %entry
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%1 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
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store i32 1, i32 addrspace(1)* %1, align 4
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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%2 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
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store i32 2, i32 addrspace(1)* %2, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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%3 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
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store i32 3, i32 addrspace(1)* %3, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb
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ret void
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}
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