8bfb2b6d77
IRTranslator lowers switches to [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. Since values and destination MBBs are included in the spv_switch intrinsics, the sequences are not needed for ISel. Before this commit, the information decoded by these sequences were added to spv_switch intrinsics in SPIRVPreLegalizer and the sequences were kept until SPIRVModuleAnalysis where they were marked skipped for emission. After this commit, the [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences and MBBs containing only these MIs are erased in SPIRVPreLegalizer. Differential Revision: https://reviews.llvm.org/D146923
21 lines
539 B
LLVM
21 lines
539 B
LLVM
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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define void @test_switch_with_unreachable_block(i1 %a) {
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%value = zext i1 %a to i32
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; CHECK-SPIRV: OpSwitch %[[#]] %[[#REACHABLE:]]
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switch i32 %value, label %unreachable [
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i32 0, label %reachable
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i32 1, label %reachable
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]
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; CHECK-SPIRV-NEXT: %[[#REACHABLE]] = OpLabel
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reachable:
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; CHECK-SPIRV-NEXT: OpReturn
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ret void
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; CHECK-SPIRV: %[[#]] = OpLabel
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; CHECK-SPIRV-NEXT: OpUnreachable
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unreachable:
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unreachable
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}
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