e7c1b4b64c
A rare case where coalescing resulted in a hh32 (high32 of high64 of vector register) subreg usage caused getSubReg() to fail as the vector reg does not have that subreg in its subregs list, but rather h32 which was expected to also act as hh32. See link below for the discussion when solving this. Patch By: critson Reviewed By: uweigand Fixes: https://github.com/llvm/llvm-project/issues/61390
83 lines
2.7 KiB
YAML
83 lines
2.7 KiB
YAML
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=greedy %s -o - \
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# RUN: | FileCheck %s
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#
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# Test that regalloc hints work for LOCRMux when a 128bit register is
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# involved.
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--- |
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; ModuleID = 'tc.ll'
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source_filename = "bugpoint-output-126c57d.bc"
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target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
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target triple = "s390x--linux-gnu"
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@g_74 = external global i32, align 4
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; Function Attrs: nounwind
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define void @main() local_unnamed_addr #0 {
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entry:
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%0 = load i32, i32* @g_74, align 4
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%conv478.i.i = sext i32 %0 to i64
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%cond.i15.i.i = lshr i32 1, 0
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%conv2.i16.i.i = zext i32 %cond.i15.i.i to i64
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%rem.i12.i.i = urem i64 %conv2.i16.i.i, %conv478.i.i
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%conv480.i.i = trunc i64 %rem.i12.i.i to i32
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%1 = icmp ult i32 %conv480.i.i, -663124367
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%rem.i.i.i = select i1 %1, i32 %conv480.i.i, i32 undef
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%tobool482.i.i = icmp eq i32 %rem.i.i.i, 0
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br i1 %tobool482.i.i, label %for.inc591.1.i.i, label %cleanup584.i.i
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cleanup584.i.i: ; preds = %entry
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unreachable
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for.inc591.1.i.i: ; preds = %entry
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unreachable
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}
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attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="z13" "target-features"="+transactional-execution,+vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.ident = !{!0}
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!0 = !{!"clang version 6.0.0"}
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...
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# CHECK: locr
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# CHECK-NOT: risblg
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---
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name: main
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64bit }
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- { id: 1, class: gr64bit }
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- { id: 2, class: gr128bit }
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- { id: 3, class: gr128bit }
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- { id: 4, class: gr64bit }
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- { id: 5, class: grx32bit }
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- { id: 6, class: grx32bit }
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- { id: 7, class: grx32bit }
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- { id: 8, class: gr128bit }
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- { id: 9, class: gr128bit }
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- { id: 10, class: gr64bit }
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body: |
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bb.0.entry:
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%0:gr64bit = LGFRL @g_74 :: (dereferenceable load (s32) from @g_74)
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undef %3.subreg_l64:gr128bit = LGHI 1
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%3.subreg_h64:gr128bit = LLILL 0
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%3:gr128bit = DLGR %3, %0
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CLFIMux %3.subreg_l32, 3631842929, implicit-def $cc
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%6:grx32bit = LOCRMux undef %6, %3.subreg_l32, 14, 4, implicit killed $cc
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CHIMux %6, 0, implicit-def $cc
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BRC 14, 8, %bb.2.for.inc591.1.i.i, implicit killed $cc
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J %bb.1.cleanup584.i.i
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bb.1.cleanup584.i.i:
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successors:
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bb.2.for.inc591.1.i.i:
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...
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