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clang-p2996/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
pvanhout 490a867f16 [GlobalISel] Also set dead flags of implicit defs added by BuildMI 
BuildMI automatically adds the implicit operands of the
instruction. This meant we couldn''t set the dead flag on
dead implicit defs in that case.

Fix it by introducing an opcode to mark a given implicit
def as dead.

Fixes #64565

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D157515
2023-08-11 08:38:37 +02:00

509 lines
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define i8 @test_i8(i32 %a, i8 %f, i8 %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi i8 [ %f, %cond.true ], [ %t, %cond.false ]
ret i8 %cond
}
define i16 @test_i16(i32 %a, i16 %f, i16 %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi i16 [ %f, %cond.true ], [ %t, %cond.false ]
ret i16 %cond
}
define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]
ret i32 %cond
}
define i64 @test_i64(i32 %a, i64 %f, i64 %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ]
ret i64 %cond
}
define float @test_float(i32 %a, float %f, float %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
ret float %cond
}
define double @test_double(i32 %a, double %f, double %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi double [ %f, %cond.true ], [ %t, %cond.false ]
ret double %cond
}
...
---
name: test_i8
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
- { id: 3, class: gpr, preferred-register: '' }
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
- { id: 7, class: gpr, preferred-register: '' }
body: |
; ALL-LABEL: name: test_i8
; ALL: bb.0.entry:
; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; ALL-NEXT: liveins: $edi, $edx, $esi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
; ALL-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.1.cond.false:
; ALL-NEXT: successors: %bb.2(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.end:
; ALL-NEXT: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
; ALL-NEXT: $al = COPY [[PHI]]
; ALL-NEXT: RET 0, implicit $al
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $edx, $esi
%0:gpr(s32) = COPY $edi
%3:gpr(s32) = COPY $esi
%1:gpr(s8) = G_TRUNC %3(s32)
%4:gpr(s32) = COPY $edx
%2:gpr(s8) = G_TRUNC %4(s32)
%5:gpr(s32) = G_CONSTANT i32 0
%8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
%6:gpr(s1) = G_TRUNC %8(s8)
G_BRCOND %6(s1), %bb.3
bb.2.cond.false:
successors: %bb.3(0x80000000)
bb.3.cond.end:
%7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1
$al = COPY %7(s8)
RET 0, implicit $al
...
---
name: test_i16
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
- { id: 3, class: gpr, preferred-register: '' }
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
- { id: 7, class: gpr, preferred-register: '' }
body: |
; ALL-LABEL: name: test_i16
; ALL: bb.0.entry:
; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; ALL-NEXT: liveins: $edi, $edx, $esi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
; ALL-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.1.cond.false:
; ALL-NEXT: successors: %bb.2(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.end:
; ALL-NEXT: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
; ALL-NEXT: $ax = COPY [[PHI]]
; ALL-NEXT: RET 0, implicit $ax
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $edx, $esi
%0:gpr(s32) = COPY $edi
%3:gpr(s32) = COPY $esi
%1:gpr(s16) = G_TRUNC %3(s32)
%4:gpr(s32) = COPY $edx
%2:gpr(s16) = G_TRUNC %4(s32)
%5:gpr(s32) = G_CONSTANT i32 0
%8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
%6:gpr(s1) = G_TRUNC %8(s8)
G_BRCOND %6(s1), %bb.3
bb.2.cond.false:
successors: %bb.3(0x80000000)
bb.3.cond.end:
%7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1
$ax = COPY %7(s16)
RET 0, implicit $ax
...
---
name: test_i32
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
- { id: 3, class: gpr, preferred-register: '' }
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
body: |
; ALL-LABEL: name: test_i32
; ALL: bb.0.entry:
; ALL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; ALL-NEXT: liveins: $edi, $edx, $esi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; ALL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
; ALL-NEXT: JCC_1 %bb.1, 5, implicit $eflags
; ALL-NEXT: JMP_1 %bb.2
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.1.cond.true:
; ALL-NEXT: successors: %bb.3(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: JMP_1 %bb.3
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.false:
; ALL-NEXT: successors: %bb.3(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.3.cond.end:
; ALL-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
; ALL-NEXT: $eax = COPY [[PHI]]
; ALL-NEXT: RET 0, implicit $eax
bb.1.entry:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
liveins: $edi, $edx, $esi
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s32) = COPY $edx
%3(s32) = G_CONSTANT i32 0
%6(s8) = G_ICMP intpred(sgt), %0(s32), %3
%4:gpr(s1) = G_TRUNC %6(s8)
G_BRCOND %4(s1), %bb.2
G_BR %bb.3
bb.2.cond.true:
successors: %bb.4(0x80000000)
G_BR %bb.4
bb.3.cond.false:
successors: %bb.4(0x80000000)
bb.4.cond.end:
%5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
$eax = COPY %5(s32)
RET 0, implicit $eax
...
---
name: test_i64
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
- { id: 2, class: gpr, preferred-register: '' }
- { id: 3, class: gpr, preferred-register: '' }
- { id: 4, class: gpr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
body: |
; ALL-LABEL: name: test_i64
; ALL: bb.0.entry:
; ALL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; ALL-NEXT: liveins: $edi, $rdx, $rsi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
; ALL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
; ALL-NEXT: JCC_1 %bb.1, 5, implicit $eflags
; ALL-NEXT: JMP_1 %bb.2
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.1.cond.true:
; ALL-NEXT: successors: %bb.3(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: JMP_1 %bb.3
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.false:
; ALL-NEXT: successors: %bb.3(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.3.cond.end:
; ALL-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
; ALL-NEXT: $rax = COPY [[PHI]]
; ALL-NEXT: RET 0, implicit $rax
bb.1.entry:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
liveins: $edi, $rdx, $rsi
%0(s32) = COPY $edi
%1(s64) = COPY $rsi
%2(s64) = COPY $rdx
%3(s32) = G_CONSTANT i32 0
%6(s8) = G_ICMP intpred(sgt), %0(s32), %3
%4:gpr(s1) = G_TRUNC %6(s8)
G_BRCOND %4(s1), %bb.2
G_BR %bb.3
bb.2.cond.true:
successors: %bb.4(0x80000000)
G_BR %bb.4
bb.3.cond.false:
successors: %bb.4(0x80000000)
bb.4.cond.end:
%5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
$rax = COPY %5(s64)
RET 0, implicit $rax
...
---
name: test_float
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
- { id: 2, class: vecr, preferred-register: '' }
- { id: 3, class: vecr, preferred-register: '' }
- { id: 4, class: vecr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
- { id: 7, class: vecr, preferred-register: '' }
- { id: 8, class: vecr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
; ALL-LABEL: name: test_float
; ALL: bb.0.entry:
; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; ALL-NEXT: liveins: $edi, $xmm0, $xmm1
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
; ALL-NEXT: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
; ALL-NEXT: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.1.cond.false:
; ALL-NEXT: successors: %bb.2(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.end:
; ALL-NEXT: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
; ALL-NEXT: $xmm0 = COPY [[COPY5]]
; ALL-NEXT: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $xmm0, $xmm1
%0:gpr(s32) = COPY $edi
%3:vecr(s128) = COPY $xmm0
%1:vecr(s32) = G_TRUNC %3(s128)
%4:vecr(s128) = COPY $xmm1
%2:vecr(s32) = G_TRUNC %4(s128)
%5:gpr(s32) = G_CONSTANT i32 0
%9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
%6:gpr(s1) = G_TRUNC %9(s8)
G_BRCOND %6(s1), %bb.3
bb.2.cond.false:
successors: %bb.3(0x80000000)
bb.3.cond.end:
%7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
%8:vecr(s128) = G_ANYEXT %7(s32)
$xmm0 = COPY %8(s128)
RET 0, implicit $xmm0
...
---
name: test_double
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: vecr, preferred-register: '' }
- { id: 2, class: vecr, preferred-register: '' }
- { id: 3, class: vecr, preferred-register: '' }
- { id: 4, class: vecr, preferred-register: '' }
- { id: 5, class: gpr, preferred-register: '' }
- { id: 6, class: gpr, preferred-register: '' }
- { id: 7, class: vecr, preferred-register: '' }
- { id: 8, class: vecr, preferred-register: '' }
body: |
; ALL-LABEL: name: test_double
; ALL: bb.0.entry:
; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; ALL-NEXT: liveins: $edi, $xmm0, $xmm1
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
; ALL-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
; ALL-NEXT: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.1.cond.false:
; ALL-NEXT: successors: %bb.2(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.end:
; ALL-NEXT: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
; ALL-NEXT: $xmm0 = COPY [[COPY5]]
; ALL-NEXT: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $xmm0, $xmm1
%0:gpr(s32) = COPY $edi
%3:vecr(s128) = COPY $xmm0
%1:vecr(s64) = G_TRUNC %3(s128)
%4:vecr(s128) = COPY $xmm1
%2:vecr(s64) = G_TRUNC %4(s128)
%5:gpr(s32) = G_CONSTANT i32 0
%9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
%6:gpr(s1) = G_TRUNC %9(s8)
G_BRCOND %6(s1), %bb.3
bb.2.cond.false:
successors: %bb.3(0x80000000)
bb.3.cond.end:
%7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1
%8:vecr(s128) = G_ANYEXT %7(s64)
$xmm0 = COPY %8(s128)
RET 0, implicit $xmm0
...
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