Craig Topper e00e20a055 [RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints. ...

These instructions requires both register operands to be compressible
so I've only applied the hint if we already have a GPRC physical register
assigned for the other register operand.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D139079

2022-12-01 11:09:38 -08:00

5.1 KiB

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