32dc1151e2
This extends the previously added uniform store case to handle stores of loop varying values to a loop invariant address. Note that the placement of this code only allows unpredicated stores; this is important for correctness. (That is "IsPredicated" is always false at this point in the function.) This patch does not include scalable types. The diff felt "large enough" as it were; I'll handle that in a separate patch. (It requires some changes to cost modeling.) Differential Revision: https://reviews.llvm.org/D133580
101 lines
5.2 KiB
LLVM
101 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -passes=loop-vectorize -S | FileCheck %s
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; Test case for PR44488. Checks that the correct predicates are created for
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; branches where true and false successors are equal. See the checks involving
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; CMP1 and CMP2.
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@v_38 = global i16 12061, align 1
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@v_39 = global i16 11333, align 1
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define i16 @test_true_and_false_branch_equal() {
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; CHECK-LABEL: @test_true_and_false_branch_equal(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_SREM_CONTINUE2:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @v_38, align 1
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[TMP0]], i32 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i16> [[BROADCAST_SPLATINSERT]], <2 x i16> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i16> [[BROADCAST_SPLAT]], zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i1> [[TMP1]], <i1 true, i1 true>
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
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; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_SREM_IF:%.*]], label [[PRED_SREM_CONTINUE:%.*]]
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; CHECK: pred.srem.if:
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; CHECK-NEXT: [[TMP4:%.*]] = srem i16 5786, [[TMP0]]
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i16> poison, i16 [[TMP4]], i32 0
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; CHECK-NEXT: br label [[PRED_SREM_CONTINUE]]
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; CHECK: pred.srem.continue:
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; CHECK-NEXT: [[TMP6:%.*]] = phi <2 x i16> [ poison, [[VECTOR_BODY]] ], [ [[TMP5]], [[PRED_SREM_IF]] ]
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
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; CHECK-NEXT: br i1 [[TMP7]], label [[PRED_SREM_IF1:%.*]], label [[PRED_SREM_CONTINUE2]]
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; CHECK: pred.srem.if1:
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; CHECK-NEXT: [[TMP8:%.*]] = srem i16 5786, [[TMP0]]
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; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i16> [[TMP6]], i16 [[TMP8]], i32 1
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; CHECK-NEXT: br label [[PRED_SREM_CONTINUE2]]
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; CHECK: pred.srem.continue2:
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; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i16> [ [[TMP6]], [[PRED_SREM_CONTINUE]] ], [ [[TMP9]], [[PRED_SREM_IF1]] ]
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> <i16 5786, i16 5786>, <2 x i16> [[TMP10]]
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; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 1
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; CHECK-NEXT: store i16 [[TMP11]], i16* @v_39, align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12
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; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 12, 12
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 111, [[MIDDLE_BLOCK]] ], [ 99, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_07:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC7:%.*]], [[FOR_LATCH:%.*]] ]
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; CHECK-NEXT: [[LV:%.*]] = load i16, i16* @v_38, align 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i16 [[LV]], 32767
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; CHECK-NEXT: br i1 [[CMP1]], label [[COND_END:%.*]], label [[COND_END]]
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; CHECK: cond.end:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i16 [[LV]], 0
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; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_LATCH]], label [[COND_FALSE4:%.*]]
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; CHECK: cond.false4:
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; CHECK-NEXT: [[REM:%.*]] = srem i16 5786, [[LV]]
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; CHECK-NEXT: br label [[FOR_LATCH]]
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; CHECK: for.latch:
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; CHECK-NEXT: [[COND6:%.*]] = phi i16 [ [[REM]], [[COND_FALSE4]] ], [ 5786, [[COND_END]] ]
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; CHECK-NEXT: store i16 [[COND6]], i16* @v_39, align 1
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; CHECK-NEXT: [[INC7]] = add nsw i16 [[I_07]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC7]], 111
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: exit:
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; CHECK-NEXT: [[RV:%.*]] = load i16, i16* @v_39, align 1
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; CHECK-NEXT: ret i16 [[RV]]
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.latch
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%i.07 = phi i16 [ 99, %entry ], [ %inc7, %for.latch ]
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%lv = load i16, i16* @v_38, align 1
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%cmp1 = icmp eq i16 %lv, 32767
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br i1 %cmp1, label %cond.end, label %cond.end
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cond.end: ; preds = %for.body, %for.body
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%cmp2 = icmp eq i16 %lv, 0
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br i1 %cmp2, label %for.latch, label %cond.false4
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cond.false4: ; preds = %cond.end
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%rem = srem i16 5786, %lv
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br label %for.latch
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for.latch: ; preds = %cond.end, %cond.false4
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%cond6 = phi i16 [ %rem, %cond.false4 ], [ 5786, %cond.end ]
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store i16 %cond6, i16* @v_39, align 1
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%inc7 = add nsw i16 %i.07, 1
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%cmp = icmp slt i16 %inc7, 111
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br i1 %cmp, label %for.body, label %exit
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exit: ; preds = %for.latch
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%rv = load i16, i16* @v_39, align 1
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ret i16 %rv
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}
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