Emmmer 0247b5aaae [LLDB][RISCV] Add riscv software breakpoint trap code ...

Added:
- Take RISC-V `ebreak` instruction as breakpoint trap code, so our breakpoint works as expected now.

Further work:
- RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
- Add support for RVC extension (the trap code, etc.).

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D131566

2022-08-11 14:26:22 +08:00

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