liqinweng c45810f810 [RISCV] When ISD::SETUGT && Imm == -1, has processed before lowering ...

When ISD::SETUGT && Imm == -1, has processed before lowering. Use assert replace it

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132373

2022-09-01 15:38:16 +08:00

508 KiB

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