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clang-p2996/llvm/test/CodeGen/RISCV
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Craig Topper 893f5e95e2 [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros. 
We can use srliw to shift out the trailing bits and slli to shift
back in zeros. The sign extend of srliw will 0 the upper 32 bits
since we will be shifting a 0 into bit 31.
2022-08-30 12:22:46 -07:00
..
GlobalISel
…
intrinsics
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rvv
[LegalizeTypes] Support widen result for VECTOR_REVERSE.
2022-08-30 10:01:26 +08:00
add-before-shl.ll
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add-imm.ll
[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
2022-06-24 08:31:52 -07:00
addc-adde-sube-subc.ll
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addcarry.ll
[test][DAGCombine] Add more tests for carry diamond. NFC
2022-01-27 00:25:26 +01:00
addimm-mulimm.ll
[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
2022-06-24 08:31:52 -07:00
addrspacecast.ll
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aext-to-sext.ll
[RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64.
2022-04-11 14:38:39 -07:00
align-loops.ll
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align.ll
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alloca.ll
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alu8.ll
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
2022-07-14 16:10:14 -07:00
alu16.ll
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
2022-07-14 16:10:14 -07:00
alu32.ll
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alu64.ll
[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
2022-02-16 09:22:11 -08:00
analyze-branch.ll
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and.ll
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
2022-08-30 12:22:46 -07:00
arith-with-overflow.ll
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atomic-cmpxchg-branch-on-result.ll
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
atomic-cmpxchg-flag.ll
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atomic-cmpxchg.ll
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atomic-fence.ll
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atomic-load-store.ll
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atomic-rmw.ll
[SDAG] try to replace subtract-from-constant with xor
2022-07-08 08:14:24 -04:00
atomic-signext.ll
[RISCV] Teach ComputeNumSignBitsForTargetNode about masked atomic intrinsics
2022-08-03 13:41:58 +01:00
attributes.ll
[RISCV] Add zihintntl instructions
2022-08-22 12:06:30 +08:00
bitreverse-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
bittest.ll
[RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)
2022-07-20 22:32:11 -07:00
blockaddress.ll
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branch-relaxation.ll
[RISCV][test] Update branch-relaxation.ll with update_llc_test_checks.py [NFC]
2022-08-25 17:01:34 +08:00
branch.ll
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bswap-bitreverse.ll
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
2022-08-30 12:22:46 -07:00
bswap-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
byval.ll
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callee-saved-fpr32s.ll
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callee-saved-fpr64s.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
callee-saved-gprs.ll
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calling-conv-half.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
calling-conv-ilp32-ilp32f-common.ll
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
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calling-conv-ilp32f-ilp32d-common.ll
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calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
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calling-conv-lp64.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-sext-zext.ll
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calling-conv-vector-float.ll
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calls.ll
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cmp-bool.ll
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codemodel-lowering.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
compress-float.ll
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compress-inline-asm.ll
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compress.ll
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copy-frameindex.mir
llvm-reduce: Don't assert on functions which don't track liveness
2022-06-07 10:00:25 -04:00
copysign-casts.ll
[RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C).
2022-06-29 09:15:09 -07:00
ctlz-cttz-ctpop.ll
[DAG] Emit table lookup from TargetLowering::expandCTTZ()
2022-08-08 12:08:05 +01:00
disable-tail-calls.ll
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disjoint.ll
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div_minsize.ll
[RISCV]Enable isIntDivCheap when attribute is minsize
2022-07-27 18:22:51 +08:00
div-by-constant.ll
[RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel.
2022-07-14 18:24:10 -07:00
div-pow2.ll
[RISCV][NFC] Use common prefix to simplify test.
2022-08-26 10:39:41 +08:00
div.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-arith-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-arith.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
double-bitmanip-dagcombines.ll
[RISCV] Select SRLI+SLLI for AND with leading ones mask
2022-03-16 02:10:57 +00:00
double-br-fcmp.ll
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
double-calling-conv.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
double-convert-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-convert.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
double-fcmp-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-fcmp.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
double-frem.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-imm.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-intrinsics-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-intrinsics.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-isnan.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-mem.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-previous-failure.ll
[RISCV] Teach combineDeMorganOfBoolean to handle (and (xor X, 1), (not Y)).
2022-08-25 10:55:45 -07:00
double-round-conv-sat.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
double-round-conv.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
double-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
double-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
double-stack-spill-restore.ll
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
dwarf-eh.ll
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early-clobber-tied-def-subreg-liveness.ll
Reland "[SplitKit] Handle early clobber + tied to def correctly"
2022-06-16 17:13:09 +08:00
early-clobber-tied-def-subreg-liveness.mir
Reland "[SplitKit] Handle early clobber + tied to def correctly"
2022-06-16 17:13:09 +08:00
eh-dwarf-cfa.ll
[RISCV] Add ISD::EH_DWARF_CFA
2022-06-08 22:03:30 +08:00
elf-preemption.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
exception-pointer-register.ll
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fastcc-float.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
fastcc-int.ll
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fixed-vectors-vadd-vp-mask.ll
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
2022-04-26 02:30:22 +00:00
fixed-vectors-vmul-vp-mask.ll
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
2022-04-26 02:30:22 +00:00
fixed-vectors-vsub-vp-mask.ll
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
2022-04-26 02:30:22 +00:00
fixups-diff.ll
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fixups-relax-diff.ll
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float-arith-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-arith.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
float-bit-preserving-dagcombines.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
float-bitmanip-dagcombines.ll
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float-br-fcmp.ll
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
float-convert-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-convert.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
float-fcmp-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-fcmp.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-frem.ll
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float-imm.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-intrinsics-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-intrinsics.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
float-isnan.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-mem.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-round-conv-sat.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
float-round-conv.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
float-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
float-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
flt-rounds.ll
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fmax-fmin.ll
[SDAG] avoid libcalls to fmin/fmax for soft-float targets
2022-03-30 11:22:03 -04:00
fold-addi-loadstore.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
fold-vector-cmp.ll
[RISCV] Enable fixed length vectors and loop vectorization with same
2022-08-26 14:45:23 -07:00
forced-atomics.ll
[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.
2022-08-21 11:48:28 -07:00
fp16-promote.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
fp128.ll
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fp-imm.ll
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fpclamptosat_vec.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
fpclamptosat.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
fpenv.ll
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frame-info.ll
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
frame.ll
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frameaddr-returnaddr.ll
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frm-dependency.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
get-register-invalid.ll
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get-register-noreserve.ll
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
get-register-reserve.ll
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get-setcc-result-type.ll
Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
2022-08-16 15:51:07 -07:00
ghccc-rv32.ll
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ghccc-rv64.ll
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half-arith-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-arith.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
half-bitmanip-dagcombines.ll
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half-br-fcmp.ll
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
half-convert-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-convert.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
half-fcmp-strict.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-fcmp.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
half-frem.ll
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half-imm.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-intrinsics.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-isnan.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-mem.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-round-conv-sat.ll
[RISCV] Use check-prefixes to reduce check lines
2022-06-06 15:59:15 +08:00
half-round-conv.ll
[RISCV] Add codegen coverage for ceil/floor/trunc/round/roundeven within FPR
2022-07-26 08:48:46 -07:00
half-select-fcmp.ll
[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
2022-08-17 09:50:08 -07:00
half-select-icmp.ll
[RISCV] Add test coverage for (select (icmp X, Y), float, float). NFC
2022-08-16 21:28:26 -07:00
hoist-global-addr-base.ll
[RISCV] Simplify test case from D130931. NFC
2022-08-01 16:50:56 -07:00
hwasan-check-memaccess.ll
[RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V
2022-08-28 21:22:13 +03:00
i32-icmp.ll
[RISCV] Use SLTIU X, -1 for (setne X, -1).
2022-08-11 15:36:04 -07:00
i64-icmp.ll
[RISCV] Use SLTIU X, -1 for (setne X, -1).
2022-08-11 15:36:04 -07:00
iabs.ll
[DAG] canCreateUndefOrPoison - add freeze(sign_extend_inreg(x,vt)) -> sign_extend_inreg(freeze(x),vt) support
2022-08-15 12:18:59 +01:00
imm-cse.ll
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imm.ll
[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.
2022-04-29 08:58:32 -07:00
indirectbr.ll
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init-array.ll
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inline-asm-abi-names.ll
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inline-asm-clobbers.ll
[RISCV] Update computeTargetABI from llc as well as clang
2022-02-24 21:55:44 -08:00
inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
2022-03-02 11:22:46 -08:00
inline-asm-f-abi-names.ll
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inline-asm-f-constraint-f.ll
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
2022-03-02 11:22:46 -08:00
inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm-S-constraint.ll
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inline-asm-zfh-constraint-f.ll
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
2022-03-02 11:22:46 -08:00
inline-asm.ll
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interrupt-attr-args-error.ll
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interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
…
interrupt-attr.ll
…
isel-optnone.ll
[RISCV] Pass OptLevel to RISCVDAGToDAGISel correctly
2022-05-30 17:22:50 -07:00
jumptable.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
large-stack.ll
[RISCV] Merge addi into load/store as there is a ADD between them
2022-04-29 04:33:05 +00:00
legalize-fneg.ll
[RISCV] Teach targetShrinkDemandedConstant to handle OR and XOR.
2022-07-17 12:36:33 -07:00
libcall-tail-calls.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
lit.local.cfg
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live-sp.mir
…
loop-strength-reduce-add-cheaper-than-mul.ll
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
2022-05-27 11:05:18 -07:00
loop-strength-reduce-loop-invar.ll
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
2022-05-27 11:05:18 -07:00
lsr-legaladdimm.ll
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machine-cp.mir
[MachineCopyPropagation][RISCV] Fix D125335 accidentally change control flow.
2022-06-17 21:40:08 -07:00
machine-cse.ll
[RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ.
2022-05-02 20:21:16 -07:00
machine-outliner-cfi.mir
[RISCV] Precommit test for D122634
2022-04-22 12:19:55 +08:00
machine-outliner-patchable.ll
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machine-outliner-position.mir
[RISCV] Precommit test for D122634
2022-04-22 12:19:55 +08:00
machine-outliner-throw.ll
[RISCV] Do not outline CFI instructions when they are needed in EH
2022-04-22 12:28:19 +08:00
machinelicm-address-pseudos.ll
[RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI
2022-08-01 11:30:02 +02:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel-lo operand.
2022-08-24 21:47:46 +08:00
machineoutliner.mir
…
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
make-compressible-for-store-address.mir
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
make-compressible-rv64.mir
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
make-compressible.mir
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
mattr-invalid-combination.ll
[RISCV] Remove check and update test file in D121183
2022-03-24 00:48:52 +08:00
mem64.ll
[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.
2022-06-30 14:20:11 -07:00
mem.ll
[RISCV] Add tests for (load (add X, [2048,4094])). NFC
2022-06-27 13:42:57 -07:00
memcpy-inline.ll
[RISCV] Teach shouldConvertConstantLoadToIntImm that constant materialization can use constant pools.
2022-07-10 14:10:17 -07:00
min-max.ll
[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.
2022-08-21 11:48:28 -07:00
mir-target-flags.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
miss-sp-restore-eh.ll
[RISCV] Fix missing stack pointer recover
2022-06-09 23:38:50 +08:00
module-target-abi2.ll
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
2022-03-24 00:48:52 +08:00
module-target-abi3.ll
[RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute
2022-08-26 14:39:39 +08:00
module-target-abi.ll
…
mul.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
musttail-call.ll
…
narrow-shl-cst.ll
[RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI.
2022-07-27 17:35:26 -07:00
neg-abs.ll
[DAGCombiner] Don't expand (neg (abs x)) if the abs has an additional user.
2022-03-01 07:32:07 -08:00
nomerge.ll
…
O0-pipeline.ll
[RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.
2022-08-01 13:44:43 -07:00
O3-pipeline.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
out-of-reach-emergency-slot.mir
…
overflow-intrinsic-optimizations.ll
…
patchable-function-entry.ll
…
pic-models.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
pr40333.ll
…
pr51206.ll
…
pr53662.mir
[RISCV] Don't getDebugLoc for the end node of MBB iterator
2022-04-30 16:00:20 +08:00
pr55201.ll
[DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.
2022-04-30 11:02:30 -07:00
pr56110.ll
[DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore.
2022-06-19 15:50:15 -07:00
pr56457.ll
[TargetLowering][RISCV] Make expandCTLZ work for non-power of 2 types.
2022-07-12 11:36:37 -07:00
prefetch.ll
[IR] Update llvm.prefetch to match docs
2022-08-19 09:11:17 +01:00
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll
Revert "[RISCV] Enable subregister liveness tracking for RVV."
2022-05-13 10:59:58 -07:00
rem.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
remat.ll
…
reserved-reg-errors.ll
…
reserved-regs.ll
…
riscv-codegenprepare-asm.ll
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
riscv-codegenprepare.ll
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
rotl-rotr.ll
[DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rotation
2022-07-26 21:14:45 +08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll
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rv32i-rv64i-half.ll
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
2022-01-29 00:01:00 +08:00
rv32zba.ll
[RISCV] Don't use li+sh3add for constants that can use lui+add.
2022-08-05 12:47:03 -07:00
rv32zbb-intrinsic.ll
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
2022-03-28 16:56:33 -07:00
rv32zbb-zbp-zbkb.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
rv32zbb.ll
[DAG] Emit table lookup from TargetLowering::expandCTTZ()
2022-08-08 12:08:05 +01:00
rv32zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbe-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbf-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv32zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbp-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv32zbp-zbkb.ll
[RISCV][NFC] Simplify tests by reorganizing check prefixes
2022-05-12 02:22:56 +00:00
rv32zbp.ll
[DAG] SimplifyDemandedBits - don't early-out for multiple use values
2022-07-27 10:54:06 +01:00
rv32zbr.ll
…
rv32zbs.ll
[RISCV] Recognize bexti from (srl (and X, 1<<C), C).
2022-07-20 15:03:52 -07:00
rv32zbt-intrinsic.ll
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
2022-03-05 21:26:51 -08:00
rv32zbt.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
rv32zknd-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv32zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv32zknh-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv32zksed-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv32zksh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64-large-stack.ll
…
rv64d-double-convert-strict.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64d-double-convert.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
rv64f-float-convert-strict.ll
[RISCV] Set target-abi explicitly to reduce codegen results
2022-06-01 13:49:23 +08:00
rv64f-float-convert.ll
[RISCV] Set target-abi explicitly to reduce codegen results
2022-06-01 13:49:23 +08:00
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Enable (srl (and X, C2), C) to form SRLIW in more cases.
2022-08-29 15:52:08 -07:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
[RISCV][NFC] Remove solved TODO for combining constant shifts
2022-05-26 09:55:19 +08:00
rv64i-shift-sext.ll
[RISCV] Relax another one use restriction in performSRACombine.
2022-08-04 14:32:31 -07:00
rv64i-single-softfloat.ll
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rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64zba.ll
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
2022-08-30 12:22:46 -07:00
rv64zbb-intrinsic.ll
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
2022-03-28 16:56:33 -07:00
rv64zbb-zbp-zbkb.ll
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
2022-07-28 14:10:44 +01:00
rv64zbb.ll
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
2022-08-30 12:22:46 -07:00
rv64zbc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbe-intrinsic.ll
…
rv64zbf-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbkb-intrinsic.ll
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
2022-01-30 12:41:09 -08:00
rv64zbkx-intrinsic.ll
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
2022-03-01 11:37:49 -08:00
rv64zbp-intrinsic.ll
[RISCV] Implement RISCVTargetLowering::getTargetConstantFromLoad.
2022-06-16 15:11:18 -07:00
rv64zbp-zbkb.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zbp.ll
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
2022-08-30 12:22:46 -07:00
rv64zbr.ll
…
rv64zbs.ll
[RISCV] Recognize bexti from (srl (and X, 1<<C), C).
2022-07-20 15:03:52 -07:00
rv64zbt-intrinsic.ll
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
2022-03-05 21:26:51 -08:00
rv64zbt.ll
[RISCV] transform MI to W variant to remove sext.w
2022-04-22 10:59:26 -07:00
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
2022-02-24 09:19:01 -08:00
rv64zfh-half-intrinsics-strict.ll
…
rv64zfh-half-intrinsics.ll
…
rv64zknd-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zknd-zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zkne-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zknh-intrinsic.ll
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
2022-07-13 19:37:34 +01:00
rv64zksed-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
rv64zksh-intrinsic.ll
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
2022-01-27 15:53:35 +08:00
sadd_sat_plus.ll
…
sadd_sat.ll
…
saverestore.ll
…
scalable-vector-struct.ll
…
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
…
select-cc.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
select-const.ll
[RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)).
2022-08-16 14:49:52 -07:00
select-constant-xor.ll
[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
2022-03-29 14:46:49 +08:00
select-optimize-multiple.ll
[RISCV] Optimize 2x SELECT for floating-point types
2022-07-11 14:10:27 +08:00
select-optimize-multiple.mir
…
select-or.ll
…
selectcc-to-shiftand.ll
[RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C).
2022-06-29 09:15:09 -07:00
setcc-logic.ll
[RISCV] Add more invertible setccs to tryDemorganOfBooleanCondition.
2022-08-29 12:23:03 -07:00
sext-zext-trunc.ll
[RISCV] Remove C!=0 restriction from (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)).
2022-08-16 14:49:52 -07:00
sextw-removal.ll
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
2022-07-28 14:10:44 +01:00
shadowcallstack.ll
…
shift-and.ll
…
shift-masked-shamt.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
shifts.ll
[RISCV] Explicitly select second operand of branch condition to X0.
2022-08-01 11:16:48 -07:00
shl-demanded.ll
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
2022-07-14 16:10:14 -07:00
shlimm-addimm.ll
…
shrinkwrap.ll
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
sink-icmp.ll
…
spill-fpr-scalar.ll
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
split-offsets.ll
[RISCV] Modify the custom isel for (add X, imm) used by load/stores.
2022-07-09 22:47:27 -07:00
split-sp-adjust.ll
…
split-udiv-by-constant.ll
[X86][RISCV] Pre-commit tests for D130862. NFC
2022-08-14 16:31:15 -07:00
split-urem-by-constant.ll
[X86][RISCV] Pre-commit tests for D130862. NFC
2022-08-14 16:31:15 -07:00
srem-lkk.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
srem-seteq-illegal-types.ll
Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
2022-08-16 15:51:07 -07:00
srem-vector-lkk.ll
…
ssub_sat_plus.ll
[RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
2022-04-13 10:01:07 +00:00
ssub_sat.ll
[RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
2022-04-13 10:01:07 +00:00
stack-folding.ll
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
[RISCV] Use two ADDIs to do some stack pointer adjustments.
2022-05-31 10:25:28 -07:00
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
…
switch-width.ll
[riscv] Add a bunch of tests exploring switch lowering
2022-05-11 13:16:31 -07:00
tail-calls.ll
…
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
trunc-free.ll
[RISCV] Enable isTruncateFree in SDAG for i64->i32 on rv64.
2022-08-15 08:32:51 -07:00
uadd_sat_plus.ll
…
uadd_sat.ll
…
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
[RISCV] Add a subtarget feature to enable unaligned scalar loads and stores
2022-05-26 15:25:47 -07:00
unfold-masked-merge-scalar-variablemask.ll
[RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
2022-04-13 10:01:07 +00:00
unroll-loop-cse.ll
Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
2022-02-17 17:27:37 +08:00
urem-lkk.ll
[RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall more libcalls
2022-08-10 10:50:29 +01:00
urem-seteq-illegal-types.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
urem-vector-lkk.ll
…
usub_sat_plus.ll
…
usub_sat.ll
…
vadd-vp-mask.ll
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
2022-04-26 02:30:22 +00:00
vararg.ll
[RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.
2022-08-30 12:22:46 -07:00
vec3-setcc-crash.ll
[RISCV] Pin a test to scalar lowering to preserve test intent [nfc]
2022-08-09 10:12:18 -07:00
vector-abi.ll
…
verify-instr.mir
…
vlenb.ll
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
2022-05-16 16:38:30 -07:00
vmul-vp-mask.ll
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
2022-04-26 02:30:22 +00:00
vsub-vp-mask.ll
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
2022-04-26 02:30:22 +00:00
wide-mem.ll
…
xaluo.ll
[RISCV] Move xori creation for scalar setccs to lowering.
2022-08-19 13:51:53 -07:00
zext-with-load-is-free.ll
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
2022-05-27 11:05:18 -07:00
zfh-half-intrinsics-strict.ll
…
zfh-half-intrinsics.ll
…
zfh-imm.ll
…
zmmul.ll
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00