ab26bd0647
Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: jfb, llvm-commits, aheejin, eraman, jgravelle-google, sbc100 Differential Revision: https://reviews.llvm.org/D50568 llvm-svn: 339474
257 lines
8.2 KiB
LLVM
257 lines
8.2 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-register-codegen-test-mode -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that basic SIMD128 arithmetic operations assemble as expected.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; ==============================================================================
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; 16 x i8
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; ==============================================================================
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; CHECK-LABEL: add_v16i8
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = add <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: sub_v16i8
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = sub <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: mul_v16i8
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = mul <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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; CHECK-LABEL: add_v8i16
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = add <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: sub_v8i16
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = sub <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: mul_v8i16
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = mul <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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; CHECK-LABEL: add_v4i32
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = add <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: sub_v4i32
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = sub <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: mul_v4i32
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = mul <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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; CHECK-LABEL: add_v2i64
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = add <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: sub_v2i64
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = sub <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: mul_v2i64
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = mul <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; ==============================================================================
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; 4 x float
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; ==============================================================================
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; CHECK-LABEL: add_v4f32
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fadd <4 x float> %x, %y
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ret <4 x float> %a
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}
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; CHECK-LABEL: sub_v4f32
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fsub <4 x float> %x, %y
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ret <4 x float> %a
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}
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; CHECK-LABEL: div_v4f32
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.div $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fdiv <4 x float> %x, %y
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ret <4 x float> %a
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}
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; CHECK-LABEL: mul_v4f32
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fmul <4 x float> %x, %y
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ret <4 x float> %a
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}
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; ==============================================================================
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; 2 x double
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; ==============================================================================
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; CHECK-LABEL: add_v2f64
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; NO-SIMD128-NOT: f64x2
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.add $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fadd <2 x double> %x, %y
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ret <2 x double> %a
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}
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; CHECK-LABEL: sub_v2f64
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; NO-SIMD128-NOT: f64x2
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fsub <2 x double> %x, %y
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ret <2 x double> %a
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}
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; CHECK-LABEL: div_v2f64
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; NO-SIMD128-NOT: f64x2
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.div $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fdiv <2 x double> %x, %y
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ret <2 x double> %a
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}
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; CHECK-LABEL: mul_v2f64
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; NO-SIMD128-NOT: f64x2
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; SIMD129-VM-NOT: f62x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
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; SIMD128: return $pop0{{$}}
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define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
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%a = fmul <2 x double> %x, %y
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ret <2 x double> %a
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}
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