6d6feaf7e3
The architectures provided to skipIf / expectedFail are regular expressions (v. _match_decorator_property() in decorators.py so on Darwin systems "arm64" would match the skips for "arm" (32-bit Linux). Update these to "arm$" to prevent this, and also update three tests (TestBuiltinFormats.py, TestCrossDSOTailCalls.py, TestCrossObjectTailCalls.py) that were skipped for arm64 via this behavior, and need to be skipped or they will fail. This was moviated by the new TestDynamicValue.py test which has an expected-fail for arm, but the test was passing on arm64 Darwin resulting in failure for the CIs.
135 lines
6.3 KiB
Python
135 lines
6.3 KiB
Python
"""Test Python APIs for setting, getting, and using address masks."""
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import os
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import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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class AddressMasksTestCase(TestBase):
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NO_DEBUG_INFO_TESTCASE = True
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def reset_all_masks(self, process):
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process.SetAddressMask(
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lldb.eAddressMaskTypeAll,
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lldb.LLDB_INVALID_ADDRESS_MASK,
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lldb.eAddressMaskRangeAll,
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)
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self.runCmd("settings set target.process.virtual-addressable-bits 0")
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self.runCmd("settings set target.process.highmem-virtual-addressable-bits 0")
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@skipIf(archs=["arm$"]) # 32-bit arm ABI hardcodes Code mask, is 32-bit
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def test_address_masks(self):
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self.build()
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(target, process, t, bp) = lldbutil.run_to_source_breakpoint(
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self, "break here", lldb.SBFileSpec("main.c")
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)
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process.SetAddressableBits(lldb.eAddressMaskTypeAll, 42)
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self.assertEqual(0x0000029500003F94, process.FixAddress(0x00265E9500003F94))
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self.reset_all_masks(process)
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# ~((1ULL<<42)-1) == 0xfffffc0000000000
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process.SetAddressMask(lldb.eAddressMaskTypeAll, 0xFFFFFC0000000000)
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self.assertEqual(0x0000029500003F94, process.FixAddress(0x00265E9500003F94))
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self.reset_all_masks(process)
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# Check that all bits can pass through unmodified
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process.SetAddressableBits(lldb.eAddressMaskTypeAll, 64)
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self.assertEqual(0x00265E9500003F94, process.FixAddress(0x00265E9500003F94))
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self.reset_all_masks(process)
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 42, lldb.eAddressMaskRangeAll
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)
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self.assertEqual(0x000002950001F694, process.FixAddress(0x00265E950001F694))
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self.assertEqual(0xFFFFFE950000F694, process.FixAddress(0xFFA65E950000F694))
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self.reset_all_masks(process)
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# Set a eAddressMaskTypeCode which has the low 3 bits marked as non-address
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# bits, confirm that they're cleared by FixAddress.
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 42, lldb.eAddressMaskRangeAll
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)
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mask = process.GetAddressMask(lldb.eAddressMaskTypeAny)
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process.SetAddressMask(lldb.eAddressMaskTypeCode, mask | 0x3)
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self.assertEqual(0x000002950001F697, process.FixAddress(0x00265E950001F697))
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self.assertEqual(0xFFFFFE950000F697, process.FixAddress(0xFFA65E950000F697))
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self.assertEqual(
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0x000002950001F697,
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process.FixAddress(0x00265E950001F697, lldb.eAddressMaskTypeData),
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)
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self.assertEqual(
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0x000002950001F694,
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process.FixAddress(0x00265E950001F697, lldb.eAddressMaskTypeCode),
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)
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self.reset_all_masks(process)
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# The user can override whatever settings the Process thinks should be used.
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 42, lldb.eAddressMaskRangeLow
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)
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self.runCmd("settings set target.process.virtual-addressable-bits 15")
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self.assertEqual(0x0000000000007694, process.FixAddress(0x00265E950001F694))
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self.assertEqual(0xFFFFFFFFFFFFF694, process.FixAddress(0xFFA65E950000F694))
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self.runCmd("settings set target.process.virtual-addressable-bits 0")
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self.assertEqual(0x000002950001F694, process.FixAddress(0x00265E950001F694))
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self.reset_all_masks(process)
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# AArch64 can have different address masks for high and low memory, when different
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# page tables are set up.
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@skipIf(archs=no_match(["arm64", "arm64e", "aarch64"]))
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@skipIf(archs=["arm$"]) # 32-bit arm ABI hardcodes Code mask, is 32-bit
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def test_address_masks_target_supports_highmem_tests(self):
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self.build()
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(target, process, t, bp) = lldbutil.run_to_source_breakpoint(
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self, "break here", lldb.SBFileSpec("main.c")
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)
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 42, lldb.eAddressMaskRangeLow
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)
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 15, lldb.eAddressMaskRangeHigh
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)
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self.assertEqual(0x000002950001F694, process.FixAddress(0x00265E950001F694))
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self.assertEqual(0xFFFFFFFFFFFFF694, process.FixAddress(0xFFA65E950000F694))
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self.reset_all_masks(process)
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# The user can override whatever settings the Process thinks should be used.
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 42, lldb.eAddressMaskRangeAll
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)
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self.runCmd("settings set target.process.virtual-addressable-bits 15")
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self.runCmd("settings set target.process.highmem-virtual-addressable-bits 15")
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self.assertEqual(0x0000000000007694, process.FixAddress(0x00265E950001F694))
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self.assertEqual(0xFFFFFFFFFFFFF694, process.FixAddress(0xFFA65E950000F694))
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self.runCmd("settings set target.process.virtual-addressable-bits 0")
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self.runCmd("settings set target.process.highmem-virtual-addressable-bits 0")
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self.assertEqual(0x000002950001F694, process.FixAddress(0x00265E950001F694))
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self.reset_all_masks(process)
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# On most targets where we have a single mask for all address range, confirm
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# that the high memory masks are ignored.
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@skipIf(archs=["arm64", "arm64e", "aarch64"])
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@skipIf(archs=["arm$"]) # 32-bit arm ABI hardcodes Code mask, is 32-bit
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def test_address_masks_target_no_highmem(self):
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self.build()
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(target, process, t, bp) = lldbutil.run_to_source_breakpoint(
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self, "break here", lldb.SBFileSpec("main.c")
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)
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 42, lldb.eAddressMaskRangeLow
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)
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process.SetAddressableBits(
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lldb.eAddressMaskTypeAll, 15, lldb.eAddressMaskRangeHigh
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)
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self.assertEqual(0x000002950001F694, process.FixAddress(0x00265E950001F694))
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self.assertEqual(0xFFFFFE950000F694, process.FixAddress(0xFFA65E950000F694))
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self.runCmd("settings set target.process.virtual-addressable-bits 15")
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self.runCmd("settings set target.process.highmem-virtual-addressable-bits 42")
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self.assertEqual(0x0000000000007694, process.FixAddress(0x00265E950001F694))
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self.assertEqual(0xFFFFFFFFFFFFF694, process.FixAddress(0xFFA65E950000F694))
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